Clock domain crossing awareness in Verilog - Step-by-Step Execution

Concept Flow - Clock domain crossing awareness

Signal in Domain A

↓

Synchronizer Stage 1

↓

Synchronizer Stage 2

↓

Signal in Domain B

↓

Use synchronized signal safely

Signal moves from one clock domain to another through two flip-flops to avoid metastability and ensure safe data transfer.

Execution Sample

Verilog

module cdc_sync(
  input wire clk_b,
  input wire async_signal_a,
  output reg sync_signal_b
);
  reg sync_stage1;

  always @(posedge clk_b) begin
    sync_stage1 <= async_signal_a;
    sync_signal_b <= sync_stage1;
  end
endmodule

This code synchronizes an asynchronous signal from clock domain A into clock domain B using two flip-flops.

Execution Table

Step	clk_b edge	async_signal_a	sync_stage1 (before)	sync_stage1 (after)	sync_signal_b (before)	sync_signal_b (after)
1	rising	0	X	0	X	X
2	rising	1	0	1	X	0
3	rising	1	1	1	0	1
4	rising	0	1	0	1	1
5	rising	0	0	0	1	0

💡 After step 5, sync_signal_b follows async_signal_a with two clock delays, ensuring safe crossing.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
async_signal_a	0	0	1	1	0	0
sync_stage1	X	0	1	1	0	0
sync_signal_b	X	X	0	1	1	0

Key Moments - 3 Insights

Why do we use two flip-flops (sync_stage1 and sync_signal_b) instead of one?

Using two flip-flops reduces the chance of metastability by giving the signal an extra clock cycle to stabilize before use, as shown in steps 2 and 3 of the execution_table.

What happens if async_signal_a changes close to clk_b's rising edge?

The first flip-flop (sync_stage1) might become metastable, but the second flip-flop (sync_signal_b) helps to resolve this, ensuring the output is stable by the next clock cycle, as seen between steps 2 and 3.

Why can't we use async_signal_a directly in domain B?

Direct use risks metastability and unreliable data because async_signal_a is not synchronized to clk_b. The synchronizer stages shown in the execution_table prevent this issue.

Visual Quiz - 3 Questions

Look at the execution_table at step 3, what is the value of sync_signal_b after the clk_b rising edge?

A 0

B X (unknown)

C 1

D async_signal_a

💡 Hint

Check the 'sync_signal_b (after)' column at step 3 in the execution_table.

At which step does sync_stage1 first capture the value 1 from async_signal_a?

A Step 1

B Step 2

C Step 3

D Step 4

💡 Hint

Look at the 'sync_stage1 (after)' column and when it changes to 1.

If we remove the second flip-flop (sync_signal_b), what risk increases?

A Metastability risk increases

B Signal delay increases

C Signal becomes synchronous

D No change

💡 Hint

Refer to the key_moments about why two flip-flops are used.

Concept Snapshot

Clock domain crossing requires synchronizing signals between different clocks.
Use two flip-flops in the receiving domain to reduce metastability.
First flip-flop captures async signal; second stabilizes it.
Avoid using async signals directly to prevent unreliable behavior.
This method adds a delay of two clock cycles in the receiving domain.

Full Transcript

This example shows how to safely transfer a signal from one clock domain to another in Verilog. The signal async_signal_a comes from domain A and is synchronized into domain B using two flip-flops: sync_stage1 and sync_signal_b. On each rising edge of clk_b, sync_stage1 captures async_signal_a, and sync_signal_b captures sync_stage1. This two-stage synchronization reduces the chance of metastability, which can cause unpredictable behavior. The execution table traces the values step-by-step, showing how the signal stabilizes after two clock cycles. Key moments explain why two flip-flops are necessary and why direct use of async signals is unsafe. The visual quiz tests understanding of signal values at different steps and the importance of the second flip-flop.

Practice

1. What is the main purpose of using a synchronizer in clock domain crossing?

easy

A. To safely transfer signals between different clock domains

B. To increase the clock frequency

C. To reduce power consumption

D. To generate a new clock signal

Solution

1. Step 1: Understand clock domain crossing

   Signals crossing from one clock domain to another can cause timing errors if not handled properly.

2. Step 2: Role of synchronizers

   Synchronizers, typically two flip-flops in series, help avoid metastability by safely transferring signals between different clock domains.

3. Final Answer:

   To safely transfer signals between different clock domains -> Option A

4. Quick Check:

   Synchronizer = Safe signal transfer [OK]

Hint: Synchronizers prevent timing errors between clocks [OK]

Common Mistakes:

• Thinking synchronizers increase clock speed
• Confusing synchronizers with power-saving methods
• Assuming synchronizers generate clocks

2. Which Verilog code snippet correctly implements a 2-flip-flop synchronizer for a single-bit signal async_signal crossing into clk domain?

easy

A. reg sync_0, sync_1; always @(posedge clk) begin sync_1 <= async_signal; sync_0 <= sync_1; end

B. reg sync_0, sync_1; always @(posedge clk) begin sync_0 <= async_signal; sync_1 <= sync_0; end

C. reg sync_0, sync_1; always @(posedge async_signal) begin sync_0 <= clk; sync_1 <= sync_0; end

D. reg sync_0, sync_1; always @(negedge clk) begin sync_0 <= async_signal; sync_1 <= sync_0; end

Solution

1. Step 1: Identify correct clock edge and signal assignment

   The synchronizer must sample the asynchronous signal on the positive edge of the destination clock (clk), so posedge clk is correct.

2. Step 2: Check flip-flop chaining order

   The first flip-flop captures async_signal, the second captures the output of the first. This is correctly done as sync_0 <= async_signal; then sync_1 <= sync_0;.

3. Final Answer:

   reg sync_0, sync_1; always @(posedge clk) begin sync_0 <= async_signal; sync_1 <= sync_0; end -> Option B

4. Quick Check:

   Correct clock edge and flip-flop order = reg sync_0, sync_1; always @(posedge clk) begin sync_0 <= async_signal; sync_1 <= sync_0; end [OK]

Hint: Use posedge clk and chain flip-flops in order [OK]

Common Mistakes:

• Using negedge instead of posedge
• Swapping flip-flop assignments
• Triggering on async_signal edge

3. Given the following Verilog code snippet crossing a signal data_in from clk_a domain to clk_b domain using a 2-flip-flop synchronizer, what is the expected output of data_sync after several clock cycles?

reg sync_0, sync_1;
always @(posedge clk_b) begin
  sync_0 <= data_in;
  sync_1 <= sync_0;
end
assign data_sync = sync_1;

medium

A. The code will cause a synthesis error

B. data_sync will always match data_in immediately

C. data_sync will never change from initial value

D. data_sync will be a delayed and synchronized version of data_in

Solution

1. Step 1: Understand synchronizer behavior

   The 2-flip-flop synchronizer delays the asynchronous input by two clock cycles of clk_b and reduces metastability risk.

2. Step 2: Analyze output data_sync

   data_sync reflects data_in but delayed and synchronized to clk_b domain, not immediate.

3. Final Answer:

   data_sync will be a delayed and synchronized version of data_in -> Option D

4. Quick Check:

   Synchronizer output = delayed synchronized signal [OK]

Hint: Synchronizer delays and syncs signals, no immediate match [OK]

Common Mistakes:

• Expecting immediate signal match
• Assuming no delay in synchronization
• Thinking code causes synthesis error

4. Identify the problem in this Verilog code crossing a multi-bit signal data_bus[7:0] from clk_a to clk_b domain:

reg [7:0] sync_0, sync_1;
always @(posedge clk_b) begin
  sync_0 <= data_bus;
  sync_1 <= sync_0;
end

medium

A. The clock edge should be negedge instead of posedge

B. The code is correct and safe for multi-bit crossing

C. Multi-bit signals require handshake or FIFO, not simple flip-flop synchronizers

D. Missing reset signals causes metastability

Solution

1. Step 1: Recognize multi-bit signal crossing issues

   Multi-bit signals crossing clock domains can cause data corruption if bits change at different times.

2. Step 2: Understand proper methods for multi-bit crossing

   Simple flip-flop synchronizers are not safe for multi-bit buses; handshake protocols or FIFOs are needed.

3. Final Answer:

   Multi-bit signals require handshake or FIFO, not simple flip-flop synchronizers -> Option C

4. Quick Check:

   Multi-bit crossing needs handshake/FIFO [OK]

Hint: Use handshake or FIFO for multi-bit signals [OK]

Common Mistakes:

• Assuming flip-flops alone are safe for buses
• Changing clock edge without reason
• Ignoring metastability risks

5. You need to transfer a 16-bit data word from clk_fast domain to clk_slow domain safely. Which method best ensures data integrity and avoids metastability?

hard

A. Use a handshake protocol with data valid and acknowledge signals

B. Directly assign the data bus without synchronization

C. Use a 2-flip-flop synchronizer on each bit individually

D. Use asynchronous reset on the data bus

Solution

1. Step 1: Consider multi-bit data crossing challenges

   Transferring 16-bit data across clock domains risks partial updates and metastability if not handled properly.

2. Step 2: Evaluate synchronization methods

   Using handshake protocols with valid and acknowledge signals ensures complete and safe data transfer between different clock domains.

3. Final Answer:

   Use a handshake protocol with data valid and acknowledge signals -> Option A

4. Quick Check:

   Handshake ensures safe multi-bit crossing [OK]

Hint: Handshake protocols ensure safe multi-bit crossing [OK]

Common Mistakes:

• Trying to synchronize each bit separately
• Ignoring synchronization and assigning directly
• Relying on asynchronous reset for crossing