Clock domain crossing awareness in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple synchronizer module

What is the output of the following Verilog code after 3 clock cycles of clk2, assuming async_signal changes from 0 to 1 at the start?

Verilog

module synchronizer(
  input wire clk2,
  input wire async_signal,
  output reg sync_signal
);
  reg sync_1;
  always @(posedge clk2) begin
    sync_1 <= async_signal;
    sync_signal <= sync_1;
  end
endmodule

A sync_signal never becomes 1

B sync_signal becomes 1 immediately at the first clk2 rising edge

C sync_signal becomes 1 after 2 clock cycles of clk2

D sync_signal becomes 1 after 1 clock cycle of clk2

💡 Hint

Think about how the two-stage synchronizer delays the async signal by two clock cycles.

The two flip-flops in series delay the async_signal by two clk2 cycles before sync_signal reflects the change, so sync_signal becomes 1 after 2 cycles.

🧠 Conceptual

intermediate

Identifying metastability risk

Which of the following signals is at risk of metastability in a clock domain crossing scenario?

A A signal generated and used within the same clock domain

B A signal sampled asynchronously without synchronization flip-flops

C A signal synchronized by two flip-flops in the destination clock domain

D A signal that is a constant logic 0 or 1

💡 Hint

Metastability occurs when a signal changes close to the clock edge without proper synchronization.

Sampling an asynchronous signal directly without synchronization flip-flops risks metastability because the flip-flop input may change near the clock edge.

🔧 Debug

advanced

Debugging a CDC handshake failure

Given the following handshake signals crossing from clk1 to clk2 domain, what is the main cause of failure?

Verilog

module handshake(
  input wire clk1,
  input wire clk2,
  input wire req_clk1,
  output reg ack_clk2
);
  reg req_sync1, req_sync2;
  always @(posedge clk2) begin
    req_sync1 <= req_clk1;
    req_sync2 <= req_sync1;
    ack_clk2 <= req_sync2;
  end
endmodule

A Missing reset signals causing unknown initial states

B ack_clk2 is assigned asynchronously without synchronization

C Using only one flip-flop for synchronization

D req_clk1 is not synchronized properly before use in clk2 domain

💡 Hint

Consider what happens to flip-flops without reset at startup.

Without reset, the flip-flops may start in unknown states causing handshake failure even if synchronization is correct.

📝 Syntax

advanced

Identify the syntax error in CDC synchronizer code

Which option contains a syntax error in this CDC synchronizer code snippet?

Verilog

always @(posedge clk) begin
  sync_1 <= async_signal;
  sync_2 <= sync_1
end

A Missing semicolon after sync_2 <= sync_1

B Incorrect sensitivity list syntax

C Using blocking assignment instead of non-blocking

D Missing begin-end block

💡 Hint

Check each line for proper statement termination.

The line 'sync_2 <= sync_1' is missing a semicolon at the end, causing a syntax error.

🚀 Application

expert

Designing a safe pulse synchronizer

You need to safely transfer a single-cycle pulse from clk1 domain to clk2 domain without missing or duplicating pulses. Which design approach is correct?

A Use a single flip-flop synchronizer on the pulse signal

B Directly sample the pulse signal in clk2 domain with a single flip-flop

C Use a combinational AND gate between clk1 and clk2 domains

D Use a toggle flip-flop in clk1 domain and detect edges in clk2 domain with a two-stage synchronizer

💡 Hint

Think about how to convert a pulse into a level signal that can be safely synchronized.

A toggle flip-flop changes state on each pulse in clk1 domain; the clk2 domain detects edges of this toggle signal after synchronization, ensuring no pulses are missed or duplicated.

Practice

1. What is the main purpose of using a synchronizer in clock domain crossing?

easy

A. To safely transfer signals between different clock domains

B. To increase the clock frequency

C. To reduce power consumption

D. To generate a new clock signal

Solution

1. Step 1: Understand clock domain crossing

   Signals crossing from one clock domain to another can cause timing errors if not handled properly.

2. Step 2: Role of synchronizers

   Synchronizers, typically two flip-flops in series, help avoid metastability by safely transferring signals between different clock domains.

3. Final Answer:

   To safely transfer signals between different clock domains -> Option A

4. Quick Check:

   Synchronizer = Safe signal transfer [OK]

Hint: Synchronizers prevent timing errors between clocks [OK]

Common Mistakes:

• Thinking synchronizers increase clock speed
• Confusing synchronizers with power-saving methods
• Assuming synchronizers generate clocks

2. Which Verilog code snippet correctly implements a 2-flip-flop synchronizer for a single-bit signal async_signal crossing into clk domain?

easy

A. reg sync_0, sync_1; always @(posedge clk) begin sync_1 <= async_signal; sync_0 <= sync_1; end

B. reg sync_0, sync_1; always @(posedge clk) begin sync_0 <= async_signal; sync_1 <= sync_0; end

C. reg sync_0, sync_1; always @(posedge async_signal) begin sync_0 <= clk; sync_1 <= sync_0; end

D. reg sync_0, sync_1; always @(negedge clk) begin sync_0 <= async_signal; sync_1 <= sync_0; end

Solution

1. Step 1: Identify correct clock edge and signal assignment

   The synchronizer must sample the asynchronous signal on the positive edge of the destination clock (clk), so posedge clk is correct.

2. Step 2: Check flip-flop chaining order

   The first flip-flop captures async_signal, the second captures the output of the first. This is correctly done as sync_0 <= async_signal; then sync_1 <= sync_0;.

3. Final Answer:

   reg sync_0, sync_1; always @(posedge clk) begin sync_0 <= async_signal; sync_1 <= sync_0; end -> Option B

4. Quick Check:

   Correct clock edge and flip-flop order = reg sync_0, sync_1; always @(posedge clk) begin sync_0 <= async_signal; sync_1 <= sync_0; end [OK]

Hint: Use posedge clk and chain flip-flops in order [OK]

Common Mistakes:

• Using negedge instead of posedge
• Swapping flip-flop assignments
• Triggering on async_signal edge

3. Given the following Verilog code snippet crossing a signal data_in from clk_a domain to clk_b domain using a 2-flip-flop synchronizer, what is the expected output of data_sync after several clock cycles?

reg sync_0, sync_1;
always @(posedge clk_b) begin
  sync_0 <= data_in;
  sync_1 <= sync_0;
end
assign data_sync = sync_1;

medium

A. The code will cause a synthesis error

B. data_sync will always match data_in immediately

C. data_sync will never change from initial value

D. data_sync will be a delayed and synchronized version of data_in

Solution

1. Step 1: Understand synchronizer behavior

   The 2-flip-flop synchronizer delays the asynchronous input by two clock cycles of clk_b and reduces metastability risk.

2. Step 2: Analyze output data_sync

   data_sync reflects data_in but delayed and synchronized to clk_b domain, not immediate.

3. Final Answer:

   data_sync will be a delayed and synchronized version of data_in -> Option D

4. Quick Check:

   Synchronizer output = delayed synchronized signal [OK]

Hint: Synchronizer delays and syncs signals, no immediate match [OK]

Common Mistakes:

• Expecting immediate signal match
• Assuming no delay in synchronization
• Thinking code causes synthesis error

4. Identify the problem in this Verilog code crossing a multi-bit signal data_bus[7:0] from clk_a to clk_b domain:

reg [7:0] sync_0, sync_1;
always @(posedge clk_b) begin
  sync_0 <= data_bus;
  sync_1 <= sync_0;
end

medium

A. The clock edge should be negedge instead of posedge

B. The code is correct and safe for multi-bit crossing

C. Multi-bit signals require handshake or FIFO, not simple flip-flop synchronizers

D. Missing reset signals causes metastability

Solution

1. Step 1: Recognize multi-bit signal crossing issues

   Multi-bit signals crossing clock domains can cause data corruption if bits change at different times.

2. Step 2: Understand proper methods for multi-bit crossing

   Simple flip-flop synchronizers are not safe for multi-bit buses; handshake protocols or FIFOs are needed.

3. Final Answer:

   Multi-bit signals require handshake or FIFO, not simple flip-flop synchronizers -> Option C

4. Quick Check:

   Multi-bit crossing needs handshake/FIFO [OK]

Hint: Use handshake or FIFO for multi-bit signals [OK]

Common Mistakes:

• Assuming flip-flops alone are safe for buses
• Changing clock edge without reason
• Ignoring metastability risks

5. You need to transfer a 16-bit data word from clk_fast domain to clk_slow domain safely. Which method best ensures data integrity and avoids metastability?

hard

A. Use a handshake protocol with data valid and acknowledge signals

B. Directly assign the data bus without synchronization

C. Use a 2-flip-flop synchronizer on each bit individually

D. Use asynchronous reset on the data bus

Solution

1. Step 1: Consider multi-bit data crossing challenges

   Transferring 16-bit data across clock domains risks partial updates and metastability if not handled properly.

2. Step 2: Evaluate synchronization methods

   Using handshake protocols with valid and acknowledge signals ensures complete and safe data transfer between different clock domains.

3. Final Answer:

   Use a handshake protocol with data valid and acknowledge signals -> Option A

4. Quick Check:

   Handshake ensures safe multi-bit crossing [OK]

Hint: Handshake protocols ensure safe multi-bit crossing [OK]

Common Mistakes:

• Trying to synchronize each bit separately
• Ignoring synchronization and assigning directly
• Relying on asynchronous reset for crossing