Clock divider design in Verilog - Mini Project: Build & Apply

Clock Divider Design

📖 Scenario: In digital electronics, a clock divider is used to reduce the frequency of a clock signal. This is useful when you need slower clock signals for different parts of a circuit.

🎯 Goal: You will create a simple clock divider module in Verilog that divides the input clock frequency by 4.

📋 What You'll Learn

Create a 2-bit counter to count clock pulses

Use the counter to generate a divided clock output

Implement the clock divider as a Verilog module named clock_divider

The module should have inputs clk and reset, and output clk_out

💡 Why This Matters

🌍 Real World

Clock dividers are used in digital circuits to generate slower clocks from a fast master clock. This helps different parts of a system run at suitable speeds.

💼 Career

Understanding clock dividers is important for hardware engineers working on FPGA or ASIC designs, where clock management is critical.

1

Create the module and declare inputs and outputs

Write a Verilog module named clock_divider with inputs clk and reset, and output clk_out. Declare clk_out as a reg type.

Verilog

module clock_divider(input clk, input reset, output reg clk_out);
// Your code here
endmodule

Hint

Start by writing the module header with the correct inputs and outputs.

2

Add a 2-bit counter register

Inside the clock_divider module, declare a 2-bit register named count to hold the counter value.

Verilog

module clock_divider(input clk, input reset, output reg clk_out);
    reg [1:0] count;
    // Your code here
endmodule

Hint

Use reg [1:0] count; to declare a 2-bit register.

3

Implement the counter and clock division logic

Add an always block triggered on the rising edge of clk or when reset is high. Inside, reset count and clk_out to 0 when reset is high. Otherwise, increment count by 1 and toggle clk_out when count reaches 3.

Verilog

module clock_divider(input clk, input reset, output reg clk_out);
    reg [1:0] count;

    always @(posedge clk or posedge reset) begin
        // Your code here
    end
endmodule

Hint

Use a synchronous reset and increment the counter on each clock. Toggle the output clock when the counter reaches 3.

4

Test the clock divider output

Write a testbench module named testbench that instantiates clock_divider. Generate a clock signal clk toggling every 5 time units. Apply a reset pulse for 10 time units at the start. Run the simulation for 50 time units and use $display to print clk_out value every positive edge of clk.

Verilog

module clock_divider(input clk, input reset, output reg clk_out);
    reg [1:0] count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            count <= 0;
            clk_out <= 0;
        end else begin
            if (count == 2'd3) begin
                count <= 0;
                clk_out <= ~clk_out;
            end else begin
                count <= count + 1;
            end
        end
    end
endmodule

module testbench;
    reg clk = 0;
    reg reset;
    wire clk_out;

    clock_divider uut(.clk(clk), .reset(reset), .clk_out(clk_out));

    always #5 clk = ~clk;

    initial begin
        reset = 1;
        #10 reset = 0;
        // Your code here
    end
endmodule

Hint

Use repeat and @(posedge clk) to print the output clock value at each rising edge.

Practice

1.

What is the main purpose of a clock divider in Verilog?

easy

A. To reset the clock signal

B. To increase the clock frequency

C. To slow down a fast clock signal by dividing its frequency

D. To generate random clock pulses

Solution

1. Step 1: Understand clock divider function

   A clock divider reduces the frequency of an input clock signal by toggling the output clock after a set number of input cycles.

2. Step 2: Identify correct purpose

   Among the options, only slowing down the clock frequency matches the clock divider's role.

3. Final Answer:

   To slow down a fast clock signal by dividing its frequency -> Option C

4. Quick Check:

   Clock divider = slows clock [OK]

Hint: Clock divider reduces frequency, not increases it [OK]

Common Mistakes:

• Confusing clock divider with clock multiplier
• Thinking clock divider resets the clock
• Assuming it generates random pulses

2.

Which of the following is the correct way to declare a 4-bit counter register in Verilog?

easy

A. reg [3:0] counter;

B. wire [4:0] counter;

C. reg counter[3:0];

D. integer counter;

Solution

1. Step 1: Understand register declaration

   In Verilog, a 4-bit register is declared as reg [3:0] name; where 3:0 means 4 bits from 3 down to 0.

2. Step 2: Check options

   reg [3:0] counter; uses reg and correct bit range. wire [4:0] counter; uses wire and wrong bit width. reg counter[3:0]; syntax is incorrect for vector registers. integer counter; declares integer, not a 4-bit register.

3. Final Answer:

   reg [3:0] counter; -> Option A

4. Quick Check:

   4-bit reg = reg [3:0] [OK]

Hint: Use reg [3:0] for 4-bit registers in Verilog [OK]

Common Mistakes:

• Using wire instead of reg for counters
• Incorrect bit range syntax
• Confusing integer with fixed bit registers

3.

Consider this Verilog snippet for a clock divider:

reg [2:0] count = 0;
reg clk_out = 0;
always @(posedge clk_in or posedge reset) begin
  if (reset) begin
    count <= 0;
    clk_out <= 0;
  end else if (count == 3) begin
    count <= 0;
    clk_out <= ~clk_out;
  end else begin
    count <= count + 1;
  end
end

What is the frequency division factor of clk_out relative to clk_in?

medium

A. 4

B. 6

C. 2

D. 8

Solution

1. Step 1: Analyze counter behavior

   The counter counts from 0 to 3, so it counts 4 input clock cycles before toggling clk_out.

2. Step 2: Calculate frequency division

   clk_out toggles every 4 cycles, so one full period of clk_out is 8 input cycles (4 cycles high, 4 cycles low). Thus, frequency is divided by 8.

3. Final Answer:

   8 -> Option D

4. Quick Check:

   Toggle every 4 cycles -> divide by 8 [OK]

Hint: Frequency division = 2 x (counter max + 1) [OK]

Common Mistakes:

• Counting only toggle cycles, not full period
• Misreading counter max value
• Ignoring clk_out toggling logic

4.

Identify the error in this clock divider code snippet:

reg [3:0] count;
reg clk_out;
always @(posedge clk_in) begin
  if (count == 7) begin
    count = 0;
    clk_out = ~clk_out;
  end else begin
    count = count + 1;
  end
end

medium

A. Missing reset condition for count and clk_out

B. Using blocking assignments (=) instead of non-blocking (<=) inside always block

C. Counter max value should be 15, not 7

D. clk_out should not toggle inside always block

Solution

1. Step 1: Check assignment types in sequential logic

   Inside an always block triggered by clock edge, non-blocking assignments (<=) should be used to avoid race conditions.

2. Step 2: Identify error in code

   The code uses blocking assignments (=) which can cause incorrect behavior in sequential logic.

3. Final Answer:

   Using blocking assignments (=) instead of non-blocking (<=) inside always block -> Option B

4. Quick Check:

   Sequential always block needs <= [OK]

Hint: Use <= for registers inside clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in clocked always blocks
• Forgetting reset logic (but not main error here)
• Incorrect max count value (not error here)

5.

You want to design a clock divider that divides the input clock frequency by 10 using a 4-bit counter. Which approach correctly achieves this?

always @(posedge clk_in or posedge reset) begin
  if (reset) begin
    count <= 0;
    clk_out <= 0;
  end else if (count == 4) begin
    count <= 0;
    clk_out <= ~clk_out;
  end else begin
    count <= count + 1;
  end
end

Choose the correct explanation.

hard

A. This code divides frequency by 10 because clk_out toggles every 5 cycles, full period 10

B. This code divides frequency by 5 because clk_out toggles every 5 cycles, full period 5

C. This code divides frequency by 8 because count max is 4, toggling twice per 8 cycles

D. This code divides frequency by 4 because count resets at 4

Solution

1. Step 1: Understand toggle and count max

   The counter counts from 0 to 4 (5 cycles). clk_out toggles after 5 input cycles.

2. Step 2: Calculate frequency division

   Since clk_out toggles every 5 cycles, one full period is 10 cycles (5 high + 5 low), so frequency divides by 10.

3. Final Answer:

   This code divides frequency by 10 because clk_out toggles every 5 cycles, full period 10 -> Option A

4. Quick Check:

   Toggle every 5 cycles -> divide by 10 [OK]

Hint: Frequency division = 2 x (count max + 1) [OK]

Common Mistakes:

• Confusing toggle count with full period
• Assuming count max is frequency division directly
• Ignoring clk_out toggling effect