Clock divider design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple clock divider

What is the output frequency of the clock signal clk_out relative to the input clock clk_in in the following Verilog code?

Verilog

module clk_div(
  input wire clk_in,
  output reg clk_out
);
  reg [1:0] count = 0;
  always @(posedge clk_in) begin
    count <= count + 1;
    if (count == 1) begin
      clk_out <= ~clk_out;
      count <= 0;
    end
  end
endmodule

A clk_out frequency is clk_in frequency divided by 4

B clk_out frequency is clk_in frequency divided by 2

C clk_out frequency is the same as clk_in frequency

D clk_out frequency is clk_in frequency divided by 3

💡 Hint

Count how many input clock cycles it takes for clk_out to toggle once.

The counter counts from 0 to 1 (2 cycles). On the 2nd cycle, clk_out toggles, so one full period of clk_out takes 4 input clock cycles (2 cycles for rising edge and 2 for falling edge). Thus, clk_out frequency is clk_in frequency divided by 4.

🧠 Conceptual

intermediate

Purpose of reset in clock divider

Why is it important to include a reset signal in a clock divider design?

A To increase the output clock frequency

B To initialize the counter and output to a known state at startup

C To reduce power consumption during operation

D To synchronize the output clock with an external signal

💡 Hint

Think about what happens to counters when the device powers on.

The reset signal sets the counter and output clock to a known starting state. Without reset, the counter may start at an unknown value causing unpredictable output clock behavior.

🔧 Debug

advanced

Identify the error in this clock divider code

What error will occur when synthesizing or simulating the following clock divider code?

Verilog

module clk_div(
  input wire clk_in,
  output reg clk_out
);
  reg [1:0] count = 0;
  always @(posedge clk_in) begin
    if (count == 4) begin
      clk_out <= ~clk_out;
      count <= 0;
    end else
      count <= count + 1;
  end
endmodule

A Count will overflow causing unexpected behavior

B Synthesis error due to missing reset signal

C Simulation error due to uninitialized clk_out

D clk_out will never toggle because count never reaches 4

💡 Hint

Check the size of the count register and the maximum value it can hold.

The count register is [1:0] (2 bits wide), so it can hold values from 0 to 3. The code checks if count == 4, which can never be true. Thus, clk_out will never toggle.

📝 Syntax

advanced

Identify the syntax error in this clock divider code

Which option correctly fixes the syntax error in the following code snippet?

Verilog

module clk_div(
  input wire clk_in,
  output reg clk_out
);
  reg [3:0] count = 0
  always @(posedge clk_in) begin
    if (count == 8) begin
      clk_out <= ~clk_out;
      count <= 0;
    end else
      count <= count + 1;
  end
endmodule

A Add a semicolon after 'reg [3:0] count = 0;'

B Remove 'begin' and 'end' keywords

C Replace 'if (count == 8)' with 'if count == 8 then'

D Change 'always @(posedge clk_in)' to 'always posedge(clk_in)'

💡 Hint

Check the line where the register is declared.

The line 'reg [3:0] count = 0' is missing a semicolon at the end. Verilog requires semicolons after declarations.

Option A is invalid syntax. Option A uses incorrect if syntax. Option A removes necessary block delimiters.

🚀 Application

expert

Calculate output frequency for parameterized clock divider

Given the following parameterized clock divider module, what is the output frequency of clk_out if the input clock clk_in is 100 MHz and parameter DIV is set to 25?

Verilog

module clk_div #(parameter DIV = 2)(
  input wire clk_in,
  output reg clk_out = 0
);
  reg [$clog2(DIV)-1:0] count = 0;
  always @(posedge clk_in) begin
    if (count == DIV-1) begin
      clk_out <= ~clk_out;
      count <= 0;
    end else
      count <= count + 1;
  end
endmodule

A 1 MHz

B 4 MHz

C 2 MHz

D 50 MHz

💡 Hint

Calculate how many input clock cycles make one full period of clk_out.

The counter counts from 0 to DIV-1 (24), toggling clk_out on the 25th cycle. One full period of clk_out is two toggles, so 2 * 25 = 50 input clock cycles.

Input frequency is 100 MHz, so output frequency is 100 MHz / 50 = 2 MHz.

Practice

1.

What is the main purpose of a clock divider in Verilog?

easy

A. To reset the clock signal

B. To increase the clock frequency

C. To slow down a fast clock signal by dividing its frequency

D. To generate random clock pulses

Solution

1. Step 1: Understand clock divider function

   A clock divider reduces the frequency of an input clock signal by toggling the output clock after a set number of input cycles.

2. Step 2: Identify correct purpose

   Among the options, only slowing down the clock frequency matches the clock divider's role.

3. Final Answer:

   To slow down a fast clock signal by dividing its frequency -> Option C

4. Quick Check:

   Clock divider = slows clock [OK]

Hint: Clock divider reduces frequency, not increases it [OK]

Common Mistakes:

• Confusing clock divider with clock multiplier
• Thinking clock divider resets the clock
• Assuming it generates random pulses

2.

Which of the following is the correct way to declare a 4-bit counter register in Verilog?

easy

A. reg [3:0] counter;

B. wire [4:0] counter;

C. reg counter[3:0];

D. integer counter;

Solution

1. Step 1: Understand register declaration

   In Verilog, a 4-bit register is declared as reg [3:0] name; where 3:0 means 4 bits from 3 down to 0.

2. Step 2: Check options

   reg [3:0] counter; uses reg and correct bit range. wire [4:0] counter; uses wire and wrong bit width. reg counter[3:0]; syntax is incorrect for vector registers. integer counter; declares integer, not a 4-bit register.

3. Final Answer:

   reg [3:0] counter; -> Option A

4. Quick Check:

   4-bit reg = reg [3:0] [OK]

Hint: Use reg [3:0] for 4-bit registers in Verilog [OK]

Common Mistakes:

• Using wire instead of reg for counters
• Incorrect bit range syntax
• Confusing integer with fixed bit registers

3.

Consider this Verilog snippet for a clock divider:

reg [2:0] count = 0;
reg clk_out = 0;
always @(posedge clk_in or posedge reset) begin
  if (reset) begin
    count <= 0;
    clk_out <= 0;
  end else if (count == 3) begin
    count <= 0;
    clk_out <= ~clk_out;
  end else begin
    count <= count + 1;
  end
end

What is the frequency division factor of clk_out relative to clk_in?

medium

A. 4

B. 6

C. 2

D. 8

Solution

1. Step 1: Analyze counter behavior

   The counter counts from 0 to 3, so it counts 4 input clock cycles before toggling clk_out.

2. Step 2: Calculate frequency division

   clk_out toggles every 4 cycles, so one full period of clk_out is 8 input cycles (4 cycles high, 4 cycles low). Thus, frequency is divided by 8.

3. Final Answer:

   8 -> Option D

4. Quick Check:

   Toggle every 4 cycles -> divide by 8 [OK]

Hint: Frequency division = 2 x (counter max + 1) [OK]

Common Mistakes:

• Counting only toggle cycles, not full period
• Misreading counter max value
• Ignoring clk_out toggling logic

4.

Identify the error in this clock divider code snippet:

reg [3:0] count;
reg clk_out;
always @(posedge clk_in) begin
  if (count == 7) begin
    count = 0;
    clk_out = ~clk_out;
  end else begin
    count = count + 1;
  end
end

medium

A. Missing reset condition for count and clk_out

B. Using blocking assignments (=) instead of non-blocking (<=) inside always block

C. Counter max value should be 15, not 7

D. clk_out should not toggle inside always block

Solution

1. Step 1: Check assignment types in sequential logic

   Inside an always block triggered by clock edge, non-blocking assignments (<=) should be used to avoid race conditions.

2. Step 2: Identify error in code

   The code uses blocking assignments (=) which can cause incorrect behavior in sequential logic.

3. Final Answer:

   Using blocking assignments (=) instead of non-blocking (<=) inside always block -> Option B

4. Quick Check:

   Sequential always block needs <= [OK]

Hint: Use <= for registers inside clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in clocked always blocks
• Forgetting reset logic (but not main error here)
• Incorrect max count value (not error here)

5.

You want to design a clock divider that divides the input clock frequency by 10 using a 4-bit counter. Which approach correctly achieves this?

always @(posedge clk_in or posedge reset) begin
  if (reset) begin
    count <= 0;
    clk_out <= 0;
  end else if (count == 4) begin
    count <= 0;
    clk_out <= ~clk_out;
  end else begin
    count <= count + 1;
  end
end

Choose the correct explanation.

hard

A. This code divides frequency by 10 because clk_out toggles every 5 cycles, full period 10

B. This code divides frequency by 5 because clk_out toggles every 5 cycles, full period 5

C. This code divides frequency by 8 because count max is 4, toggling twice per 8 cycles

D. This code divides frequency by 4 because count resets at 4

Solution

1. Step 1: Understand toggle and count max

   The counter counts from 0 to 4 (5 cycles). clk_out toggles after 5 input cycles.

2. Step 2: Calculate frequency division

   Since clk_out toggles every 5 cycles, one full period is 10 cycles (5 high + 5 low), so frequency divides by 10.

3. Final Answer:

   This code divides frequency by 10 because clk_out toggles every 5 cycles, full period 10 -> Option A

4. Quick Check:

   Toggle every 5 cycles -> divide by 10 [OK]

Hint: Frequency division = 2 x (count max + 1) [OK]

Common Mistakes:

• Confusing toggle count with full period
• Assuming count max is frequency division directly
• Ignoring clk_out toggling effect