What is Verilog - Hands-On Activity

What is Verilog

📖 Scenario: Imagine you want to design a simple digital circuit like a light switch that turns a light on or off. To tell a computer how to build this circuit, you use a special language called Verilog.

🎯 Goal: Learn what Verilog is and create a very simple Verilog module that represents a light switch turning a light on or off.

📋 What You'll Learn

Understand that Verilog is a language to describe digital circuits

Create a simple Verilog module named LightSwitch

Use an input signal called switch and an output signal called light

Assign the output light to be the same as the input switch

💡 Why This Matters

🌍 Real World

Verilog is used by engineers to design chips inside computers, phones, and many electronic devices.

💼 Career

Knowing Verilog helps you work in hardware design, creating circuits that run faster and use less power.

1

Create a Verilog module named LightSwitch

Write a Verilog module named LightSwitch with no inputs or outputs yet.

Verilog

module LightSwitch();
// Your code here
endmodule

Hint

A Verilog module starts with module and ends with endmodule.

2

Add input and output signals

Inside the LightSwitch module, add an input signal called switch and an output signal called light.

Verilog

module LightSwitch(input switch, output light);
// Your code here
endmodule

Hint

Inputs and outputs are declared inside the parentheses after the module name.

3

Assign output light to input switch

Inside the LightSwitch module, assign the output light to be the same as the input switch using an assign statement.

Verilog

module LightSwitch(input switch, output light);
// Your code here
endmodule

Hint

Use assign light = switch; to connect the output to the input.

4

Display the Verilog module

Print the entire LightSwitch module code as a string to show the final Verilog code.

Verilog

// Your code here

Hint

Use $display to print the Verilog code as text.

Practice

1. What is Verilog primarily used for?

easy

A. Describing and designing digital circuits

B. Writing web pages

C. Creating mobile apps

D. Managing databases

Solution

1. Step 1: Understand Verilog's purpose

   Verilog is a hardware description language used to model electronic systems.

2. Step 2: Compare options with Verilog's use

   Only Describing and designing digital circuits matches the use of Verilog for digital circuit design.

3. Final Answer:

   Describing and designing digital circuits -> Option A

4. Quick Check:

   Verilog = Digital circuit design [OK]

Hint: Remember: Verilog is for hardware, not software [OK]

Common Mistakes:

• Confusing Verilog with programming languages for apps
• Thinking Verilog is for web development
• Assuming Verilog manages databases

2. Which of the following is the correct way to start a Verilog module?

easy

A. program my_module(input a, output b);

B. module my_module(input a, output b);

C. class my_module(input a, output b);

D. function my_module(input a, output b);

Solution

1. Step 1: Identify Verilog module syntax

   Verilog modules start with the keyword 'module' followed by the module name and port list.

2. Step 2: Check each option's keyword

   Only module my_module(input a, output b); uses 'module' correctly; others use keywords from different languages or contexts.

3. Final Answer:

   module my_module(input a, output b); -> Option B

4. Quick Check:

   Verilog module starts with 'module' [OK]

Hint: Modules always start with 'module' keyword [OK]

Common Mistakes:

• Using 'function' or 'class' instead of 'module'
• Confusing Verilog with software programming syntax
• Omitting the 'module' keyword

3. What will be the output of this Verilog code snippet?

module test(input wire a, output wire b);
assign b = a;
endmodule

medium

A. Output b will be the same as input a

B. Output b will always be 0

C. Output b will always be 1

D. Syntax error due to missing semicolon

Solution

1. Step 1: Understand the assign statement

   The line 'assign b = a;' connects output b directly to input a, so b follows a's value.

2. Step 2: Analyze output behavior

   Since b is assigned the value of a, b will always be the same as a.

3. Final Answer:

   Output b will be the same as input a -> Option A

4. Quick Check:

   assign b = a means b equals a [OK]

Hint: assign connects output to input directly [OK]

Common Mistakes:

• Thinking output is always 0 or 1
• Assuming syntax error due to semicolon
• Confusing assign with procedural assignment

4. Identify the error in this Verilog module:

module example(input a, output b)
assign b = a;
endmodule

medium

A. Input and output must be declared as reg

B. Incorrect use of assign statement

C. endmodule keyword is missing

D. Missing semicolon after module declaration

Solution

1. Step 1: Check module declaration syntax

   The module declaration line must end with a semicolon ';' after the port list.

2. Step 2: Verify other parts

   The assign statement and endmodule are correct; inputs and outputs can be wires by default.

3. Final Answer:

   Missing semicolon after module declaration -> Option D

4. Quick Check:

   Module header needs ';' [OK]

Hint: Module header line must end with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after module ports
• Thinking assign statement is wrong
• Assuming inputs/outputs must be reg

5. You want to create a Verilog module named led_control that has one input switch and one output led. Which of the following is the correct complete module header and port declaration?

hard

A. module led_control(input switch output led);

B. module led_control(switch input, led output);

C. module led_control(input wire switch, output wire led);

D. module led_control(input wire switch output wire led);

Solution

1. Step 1: Recall correct port declaration syntax

   Ports are declared with direction (input/output) and type (wire/reg). The correct syntax is 'input wire name'.

2. Step 2: Check each option's syntax

   module led_control(input wire switch, output wire led); correctly uses 'input wire switch, output wire led' with commas and semicolon. Others have wrong order, missing commas, or missing keywords.

3. Final Answer:

   module led_control(input wire switch, output wire led); -> Option C

4. Quick Check:

   Ports declared as 'input wire name' separated by commas [OK]

Hint: Use 'input wire name' and separate ports with commas [OK]

Common Mistakes:

• Swapping input/output keywords
• Omitting commas between ports
• Missing 'wire' keyword or semicolon