What is Verilog - Practice Questions & Exercises

Challenge - 5 Problems

🧠 Conceptual

intermediate

What is Verilog used for?

Which of the following best describes the primary use of Verilog?

A A language to create mobile apps

B A language to design and simulate digital circuits

C A language to write web pages

D A language to manage databases

💡 Hint

Think about hardware and electronics.

Verilog is mainly used to describe and simulate digital electronic circuits.

❓ Predict Output

intermediate

Verilog module output behavior

What will be the output of this Verilog module when input a is 1 and b is 0?

Verilog

module simple_and(input a, input b, output y);
  assign y = a & b;
endmodule

A y = 0

B y = a

C y = b

D y = 1

💡 Hint

AND gate outputs 1 only if both inputs are 1.

The AND operation outputs 1 only when both inputs are 1. Here, a=1 and b=0, so output y=0.

🔧 Debug

advanced

Identify the error in Verilog code

What error will this Verilog code produce?

Verilog

module error_example(input a, output reg y);
  always @ (a) begin
    if (a == 1)
      y = 1;
    else
      y = 0;
  end
endmodule

A No error, code runs fine

B Runtime error due to wrong sensitivity list

C Syntax error due to missing semicolon

D Type error due to wrong variable declaration

💡 Hint

Check the lines carefully for punctuation.

The else statement line is missing a semicolon at the end, causing a syntax error.

📝 Syntax

advanced

Correct Verilog syntax for module declaration

Which option shows the correct syntax to declare a Verilog module named my_module with inputs clk, rst and output out?

A

module my_module(input clk, input rst, output out);
endmodule

B

module my_module(input clk, rst, output out);
endmodule

C

module my_module(clk, rst, output out);
  input clk, rst;
endmodule

D

module my_module(clk, rst, out);
  input clk, rst;
  output out;
endmodule

💡 Hint

Modern Verilog allows declaring input/output types in the module header.

Option A uses the correct modern syntax with input and output declared in the module header.

🚀 Application

expert

How many bits wide is the output?

Consider this Verilog code snippet:

module adder(input [3:0] a, input [3:0] b, output [4:0] sum);
  assign sum = a + b;
endmodule

How many bits wide is the output sum and why?

A 4 bits, same as inputs because sum width matches inputs

B 6 bits, to allow extra space for overflow

C 3 bits, because sum is smaller than inputs

D 5 bits, to hold the sum including possible carry out

💡 Hint

Think about what happens when adding two 4-bit numbers.

Adding two 4-bit numbers can produce a 5-bit result to include carry out, so output sum is 5 bits wide.

Practice

1. What is Verilog primarily used for?

easy

A. Describing and designing digital circuits

B. Writing web pages

C. Creating mobile apps

D. Managing databases

Solution

1. Step 1: Understand Verilog's purpose

   Verilog is a hardware description language used to model electronic systems.

2. Step 2: Compare options with Verilog's use

   Only Describing and designing digital circuits matches the use of Verilog for digital circuit design.

3. Final Answer:

   Describing and designing digital circuits -> Option A

4. Quick Check:

   Verilog = Digital circuit design [OK]

Hint: Remember: Verilog is for hardware, not software [OK]

Common Mistakes:

• Confusing Verilog with programming languages for apps
• Thinking Verilog is for web development
• Assuming Verilog manages databases

2. Which of the following is the correct way to start a Verilog module?

easy

A. program my_module(input a, output b);

B. module my_module(input a, output b);

C. class my_module(input a, output b);

D. function my_module(input a, output b);

Solution

1. Step 1: Identify Verilog module syntax

   Verilog modules start with the keyword 'module' followed by the module name and port list.

2. Step 2: Check each option's keyword

   Only module my_module(input a, output b); uses 'module' correctly; others use keywords from different languages or contexts.

3. Final Answer:

   module my_module(input a, output b); -> Option B

4. Quick Check:

   Verilog module starts with 'module' [OK]

Hint: Modules always start with 'module' keyword [OK]

Common Mistakes:

• Using 'function' or 'class' instead of 'module'
• Confusing Verilog with software programming syntax
• Omitting the 'module' keyword

3. What will be the output of this Verilog code snippet?

module test(input wire a, output wire b);
assign b = a;
endmodule

medium

A. Output b will be the same as input a

B. Output b will always be 0

C. Output b will always be 1

D. Syntax error due to missing semicolon

Solution

1. Step 1: Understand the assign statement

   The line 'assign b = a;' connects output b directly to input a, so b follows a's value.

2. Step 2: Analyze output behavior

   Since b is assigned the value of a, b will always be the same as a.

3. Final Answer:

   Output b will be the same as input a -> Option A

4. Quick Check:

   assign b = a means b equals a [OK]

Hint: assign connects output to input directly [OK]

Common Mistakes:

• Thinking output is always 0 or 1
• Assuming syntax error due to semicolon
• Confusing assign with procedural assignment

4. Identify the error in this Verilog module:

module example(input a, output b)
assign b = a;
endmodule

medium

A. Input and output must be declared as reg

B. Incorrect use of assign statement

C. endmodule keyword is missing

D. Missing semicolon after module declaration

Solution

1. Step 1: Check module declaration syntax

   The module declaration line must end with a semicolon ';' after the port list.

2. Step 2: Verify other parts

   The assign statement and endmodule are correct; inputs and outputs can be wires by default.

3. Final Answer:

   Missing semicolon after module declaration -> Option D

4. Quick Check:

   Module header needs ';' [OK]

Hint: Module header line must end with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after module ports
• Thinking assign statement is wrong
• Assuming inputs/outputs must be reg

5. You want to create a Verilog module named led_control that has one input switch and one output led. Which of the following is the correct complete module header and port declaration?

hard

A. module led_control(input switch output led);

B. module led_control(switch input, led output);

C. module led_control(input wire switch, output wire led);

D. module led_control(input wire switch output wire led);

Solution

1. Step 1: Recall correct port declaration syntax

   Ports are declared with direction (input/output) and type (wire/reg). The correct syntax is 'input wire name'.

2. Step 2: Check each option's syntax

   module led_control(input wire switch, output wire led); correctly uses 'input wire switch, output wire led' with commas and semicolon. Others have wrong order, missing commas, or missing keywords.

3. Final Answer:

   module led_control(input wire switch, output wire led); -> Option C

4. Quick Check:

   Ports declared as 'input wire name' separated by commas [OK]

Hint: Use 'input wire name' and separate ports with commas [OK]

Common Mistakes:

• Swapping input/output keywords
• Omitting commas between ports
• Missing 'wire' keyword or semicolon