Testbench module structure in Verilog - Mini Project: Build & Apply

Testbench Module Structure in Verilog

📖 Scenario: You are designing a simple digital circuit and want to test it using a testbench. A testbench is a special module in Verilog that helps you check if your design works correctly by applying inputs and observing outputs.

🎯 Goal: Build a basic testbench module structure in Verilog that declares inputs and outputs as registers and wires, instantiates the design under test (DUT), and applies a simple stimulus.

📋 What You'll Learn

Create a testbench module named tb_simple

Declare a register clk and a register reset

Declare a wire out_signal

Instantiate a module named simple_module with ports clk, reset, and out_signal

Initialize clk to 0 and toggle it every 5 time units

Apply a reset pulse at the start

💡 Why This Matters

🌍 Real World

Testbenches are used by hardware engineers to verify that digital circuits behave correctly before manufacturing.

💼 Career

Knowing how to write testbenches is essential for FPGA and ASIC design engineers to ensure their designs work as intended.

1

Create the testbench module and declare signals

Create a Verilog module named tb_simple. Inside it, declare a reg clk, a reg reset, and a wire out_signal.

Verilog

module tb_simple();
  // Your code here
endmodule

Hint

Remember, inputs you drive in a testbench are usually reg, and outputs from the DUT are wire.

2

Instantiate the design under test (DUT)

Inside the tb_simple module, instantiate a module named simple_module with instance name dut. Connect its ports clk, reset, and out_signal to the signals declared in the testbench.

Verilog

module tb_simple();
  reg clk;
  reg reset;
  wire out_signal;

  // Instantiate simple_module here
  // Your code here
endmodule

Hint

Use named port connections to connect signals clearly.

3

Create a clock signal that toggles every 5 time units

Inside the tb_simple module, initialize clk to 0. Use an always block with a delay of 5 time units to toggle clk continuously.

Verilog

module tb_simple();
  reg clk;
  reg reset;
  wire out_signal;

  simple_module dut(
    .clk(clk),
    .reset(reset),
    .out_signal(out_signal)
  );

  // Create clock signal
  // Your code here
endmodule

Hint

The always block with #5 delay toggles the clock every 5 time units.

4

Apply a reset pulse and finish simulation

Inside the tb_simple module, create an initial block that sets reset to 1 at time 0, then sets it to 0 after 10 time units. After 100 time units, end the simulation with $finish;. Also, add a $monitor statement to print clk, reset, and out_signal values.

Verilog

module tb_simple();
  reg clk;
  reg reset;
  wire out_signal;

  simple_module dut(
    .clk(clk),
    .reset(reset),
    .out_signal(out_signal)
  );

  initial clk = 0;
  always #5 clk = ~clk;

  // Apply reset pulse and monitor signals
  // Your code here
endmodule

Hint

The initial block sets reset high, then low after 10 units. The $monitor prints signal changes. $finish ends simulation.

Practice

1. What is the main purpose of a testbench module in Verilog?

easy

A. To simulate and verify the behavior of a design module

B. To synthesize the hardware design for FPGA

C. To define input/output ports for the design

D. To optimize the design for speed

Solution

1. Step 1: Understand the role of a testbench

   A testbench is used to simulate and verify how a design behaves before hardware implementation.

2. Step 2: Differentiate from synthesis and design definition

   It does not synthesize hardware or define ports; it only tests the design by applying inputs and checking outputs.

3. Final Answer:

   To simulate and verify the behavior of a design module -> Option A

4. Quick Check:

   Testbench = simulation and verification [OK]

Hint: Testbench runs simulations, not synthesis or hardware creation [OK]

Common Mistakes:

• Confusing testbench with synthesis module
• Thinking testbench defines ports for hardware
• Assuming testbench optimizes design

2. Which of the following is the correct way to declare a testbench module in Verilog?

easy

A. module testbench(input clk, output result); endmodule

B. module testbench(input clk); endmodule

C. module testbench(); endmodule

D. module testbench(output result); endmodule

Solution

1. Step 1: Recall testbench port requirements

   A testbench usually has no ports because it internally generates signals and drives the design under test.

2. Step 2: Check each option for ports

   Only module testbench(); endmodule declares a module with no ports, which is typical for testbenches.

3. Final Answer:

   module testbench(); endmodule -> Option C

4. Quick Check:

   Testbench has no ports = module testbench(); endmodule [OK]

Hint: Testbenches usually have empty port lists () [OK]

Common Mistakes:

• Adding input/output ports to testbench module
• Confusing testbench with design module ports
• Forgetting to close module declaration

3. Given the following testbench snippet, what will be printed during simulation?

module testbench();
  reg clk = 0;
  initial begin
    $monitor("Time=%0t clk=%b", $time, clk);
    #5 clk = 1;
    #5 clk = 0;
    #5 $finish;
  end
endmodule

medium

A. Time=0 clk=0 only

B. Time=0 clk=1\nTime=5 clk=0\nTime=10 clk=1

C. No output because $monitor is missing parentheses

D. Time=0 clk=0\nTime=5 clk=1\nTime=10 clk=0

Solution

1. Step 1: Understand $monitor behavior

   $monitor prints the message whenever any listed variable changes, starting at time 0.

2. Step 2: Trace clk changes and times

   Initially clk=0 at time 0, then clk=1 at time 5, clk=0 at time 10, then simulation ends at 15.

3. Final Answer:

   Time=0 clk=0\nTime=5 clk=1\nTime=10 clk=0 -> Option D

4. Quick Check:

   $monitor prints on changes = Time=0 clk=0\nTime=5 clk=1\nTime=10 clk=0 [OK]

Hint: Trace signal changes and $monitor prints at each change [OK]

Common Mistakes:

• Confusing $monitor with $display (only prints once)
• Ignoring initial value print at time 0
• Misreading timing delays (#5)

4. Identify the error in this testbench code snippet:

module testbench();
  reg clk;
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end
endmodule

medium

A. Using forever inside initial block is not allowed

B. No error; code is correct

C. Missing semicolon after forever statement

D. clk should be declared as wire, not reg

Solution

1. Step 1: Check syntax of forever inside initial

   Using forever inside an initial block to toggle clk is valid and common for clock generation.

2. Step 2: Verify reg declaration and semicolons

   clk is correctly declared as reg, and semicolons are properly placed.

3. Final Answer:

   No error; code is correct -> Option B

4. Quick Check:

   forever in initial with reg clk = correct [OK]

Hint: forever loops inside initial are valid for clocks [OK]

Common Mistakes:

• Thinking forever is illegal inside initial
• Confusing reg and wire for clock signals
• Missing semicolons elsewhere (not here)

5. You want to create a testbench that applies a reset signal for 10 time units, then releases it, and monitors a 4-bit output signal out. Which code snippet correctly implements this behavior?

hard

A. module tb();
reg reset = 1;
wire [3:0] out;
design dut(.reset(reset), .out(out));
initial begin
#10 reset = 0;
$monitor("out=%b", out);
end
endmodule

B. module tb();
reg reset;
wire [3:0] out;
design dut(.reset(reset), .out(out));
initial begin
reset = 0;
#10 reset = 1;
$monitor("out=%b", out);
end
endmodule

C. module tb();
reg reset = 0;
wire [3:0] out;
design dut(.reset(reset), .out(out));
initial begin
#10 reset = 1;
$monitor("out=%b", out);
end
endmodule

D. module tb();
reg reset = 1;
wire [3:0] out;
design dut(.reset(reset), .out(out));
initial begin
#5 reset = 0;
$monitor("out=%b", out);
end
endmodule

Solution

1. Step 1: Check initial reset value and timing

   Reset should start at 1 (active), then after 10 time units go to 0 (inactive). Only module tb(); reg reset = 1; wire [3:0] out; design dut(.reset(reset), .out(out)); initial begin #10 reset = 0; $monitor("out=%b", out); end endmodule does this correctly.

2. Step 2: Confirm $monitor usage and signal connections

   $monitor is called after reset release to watch output changes; design instance connects reset and out signals properly.

3. Final Answer:

   module tb(); reg reset = 1; wire [3:0] out; design dut(.reset(reset), .out(out)); initial begin #10 reset = 0; $monitor("out=%b", out); end endmodule -> Option A

4. Quick Check:

   Reset active 10 units then release + monitor = module tb(); reg reset = 1; wire [3:0] out; design dut(.reset(reset), .out(out)); initial begin #10 reset = 0; $monitor("out=%b", out); end endmodule [OK]

Hint: Start reset=1, delay 10, then reset=0, monitor output [OK]

Common Mistakes:

• Setting reset low initially instead of high
• Delaying reset assertion instead of deassertion
• Placing $monitor before reset release