Testbench module structure in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple testbench module

What is the output of this Verilog testbench when simulated?

Verilog

module tb();
  reg clk = 0;
  initial begin
    $display("Start simulation");
    #5 clk = 1;
    #5 clk = 0;
    $display("End simulation");
    $finish;
  end
endmodule

A

Start simulation
End simulation

B Start simulation

C End simulation

D No output

💡 Hint

Look at the $display statements and the delays.

The testbench prints 'Start simulation' immediately, then after 10 time units prints 'End simulation' before finishing.

🧠 Conceptual

intermediate

Purpose of initial and always blocks in testbench

In a Verilog testbench, what is the main difference between an initial block and an always block?

A Both run once at start but initial is faster

B Initial runs repeatedly; always runs once at start

C Initial runs once at start; always runs repeatedly during simulation

D Both run repeatedly but initial has higher priority

💡 Hint

Think about how simulation time flows and how these blocks behave.

Initial blocks execute once at simulation start. Always blocks loop forever, reacting to events or delays.

🔧 Debug

advanced

Identify the error in this testbench module

What error will this Verilog testbench code cause when simulated?

Verilog

module tb();
  reg clk;
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end
  initial begin
    #20 $finish;
  end
endmodule

A Syntax error: 'forever' used incorrectly

B Runtime error: multiple initial blocks not allowed

C Simulation runs forever, never finishes

D No error, simulation finishes after 20 time units

💡 Hint

Check how 'forever' and multiple initial blocks behave.

Multiple initial blocks are allowed. 'forever' loops inside initial block. The second initial block ends simulation after 20 units.

📝 Syntax

advanced

Which testbench code snippet has a syntax error?

Identify the code snippet that will cause a syntax error in Verilog testbench.

A initial forever #5 clk = ~clk;

B initial begin clk = 0 #10 clk = 1; end

C always #5 clk = ~clk;

D initial begin clk = 0; #10 clk = 1; end

💡 Hint

Look carefully for missing semicolons or keywords.

Option B misses a semicolon after 'clk = 0' causing syntax error.

🚀 Application

expert

Number of clock cycles generated by this testbench

How many complete clock cycles does this testbench generate before finishing?

Verilog

module tb();
  reg clk = 0;
  initial begin
    forever #3 clk = ~clk;
  end
  initial begin
    #30 $finish;
  end
endmodule

A 5 complete clock cycles

B 10 complete clock cycles

C 15 complete clock cycles

D 20 complete clock cycles

💡 Hint

Calculate clock period and total simulation time.

Clock toggles every 3 time units, so period is 6 units. Simulation ends at 30 units. 30/6 = 5 cycles.

Practice

1. What is the main purpose of a testbench module in Verilog?

easy

A. To simulate and verify the behavior of a design module

B. To synthesize the hardware design for FPGA

C. To define input/output ports for the design

D. To optimize the design for speed

Solution

1. Step 1: Understand the role of a testbench

   A testbench is used to simulate and verify how a design behaves before hardware implementation.

2. Step 2: Differentiate from synthesis and design definition

   It does not synthesize hardware or define ports; it only tests the design by applying inputs and checking outputs.

3. Final Answer:

   To simulate and verify the behavior of a design module -> Option A

4. Quick Check:

   Testbench = simulation and verification [OK]

Hint: Testbench runs simulations, not synthesis or hardware creation [OK]

Common Mistakes:

• Confusing testbench with synthesis module
• Thinking testbench defines ports for hardware
• Assuming testbench optimizes design

2. Which of the following is the correct way to declare a testbench module in Verilog?

easy

A. module testbench(input clk, output result); endmodule

B. module testbench(input clk); endmodule

C. module testbench(); endmodule

D. module testbench(output result); endmodule

Solution

1. Step 1: Recall testbench port requirements

   A testbench usually has no ports because it internally generates signals and drives the design under test.

2. Step 2: Check each option for ports

   Only module testbench(); endmodule declares a module with no ports, which is typical for testbenches.

3. Final Answer:

   module testbench(); endmodule -> Option C

4. Quick Check:

   Testbench has no ports = module testbench(); endmodule [OK]

Hint: Testbenches usually have empty port lists () [OK]

Common Mistakes:

• Adding input/output ports to testbench module
• Confusing testbench with design module ports
• Forgetting to close module declaration

3. Given the following testbench snippet, what will be printed during simulation?

module testbench();
  reg clk = 0;
  initial begin
    $monitor("Time=%0t clk=%b", $time, clk);
    #5 clk = 1;
    #5 clk = 0;
    #5 $finish;
  end
endmodule

medium

A. Time=0 clk=0 only

B. Time=0 clk=1\nTime=5 clk=0\nTime=10 clk=1

C. No output because $monitor is missing parentheses

D. Time=0 clk=0\nTime=5 clk=1\nTime=10 clk=0

Solution

1. Step 1: Understand $monitor behavior

   $monitor prints the message whenever any listed variable changes, starting at time 0.

2. Step 2: Trace clk changes and times

   Initially clk=0 at time 0, then clk=1 at time 5, clk=0 at time 10, then simulation ends at 15.

3. Final Answer:

   Time=0 clk=0\nTime=5 clk=1\nTime=10 clk=0 -> Option D

4. Quick Check:

   $monitor prints on changes = Time=0 clk=0\nTime=5 clk=1\nTime=10 clk=0 [OK]

Hint: Trace signal changes and $monitor prints at each change [OK]

Common Mistakes:

• Confusing $monitor with $display (only prints once)
• Ignoring initial value print at time 0
• Misreading timing delays (#5)

4. Identify the error in this testbench code snippet:

module testbench();
  reg clk;
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end
endmodule

medium

A. Using forever inside initial block is not allowed

B. No error; code is correct

C. Missing semicolon after forever statement

D. clk should be declared as wire, not reg

Solution

1. Step 1: Check syntax of forever inside initial

   Using forever inside an initial block to toggle clk is valid and common for clock generation.

2. Step 2: Verify reg declaration and semicolons

   clk is correctly declared as reg, and semicolons are properly placed.

3. Final Answer:

   No error; code is correct -> Option B

4. Quick Check:

   forever in initial with reg clk = correct [OK]

Hint: forever loops inside initial are valid for clocks [OK]

Common Mistakes:

• Thinking forever is illegal inside initial
• Confusing reg and wire for clock signals
• Missing semicolons elsewhere (not here)

5. You want to create a testbench that applies a reset signal for 10 time units, then releases it, and monitors a 4-bit output signal out. Which code snippet correctly implements this behavior?

hard

A. module tb();
reg reset = 1;
wire [3:0] out;
design dut(.reset(reset), .out(out));
initial begin
#10 reset = 0;
$monitor("out=%b", out);
end
endmodule

B. module tb();
reg reset;
wire [3:0] out;
design dut(.reset(reset), .out(out));
initial begin
reset = 0;
#10 reset = 1;
$monitor("out=%b", out);
end
endmodule

C. module tb();
reg reset = 0;
wire [3:0] out;
design dut(.reset(reset), .out(out));
initial begin
#10 reset = 1;
$monitor("out=%b", out);
end
endmodule

D. module tb();
reg reset = 1;
wire [3:0] out;
design dut(.reset(reset), .out(out));
initial begin
#5 reset = 0;
$monitor("out=%b", out);
end
endmodule

Solution

1. Step 1: Check initial reset value and timing

   Reset should start at 1 (active), then after 10 time units go to 0 (inactive). Only module tb(); reg reset = 1; wire [3:0] out; design dut(.reset(reset), .out(out)); initial begin #10 reset = 0; $monitor("out=%b", out); end endmodule does this correctly.

2. Step 2: Confirm $monitor usage and signal connections

   $monitor is called after reset release to watch output changes; design instance connects reset and out signals properly.

3. Final Answer:

   module tb(); reg reset = 1; wire [3:0] out; design dut(.reset(reset), .out(out)); initial begin #10 reset = 0; $monitor("out=%b", out); end endmodule -> Option A

4. Quick Check:

   Reset active 10 units then release + monitor = module tb(); reg reset = 1; wire [3:0] out; design dut(.reset(reset), .out(out)); initial begin #10 reset = 0; $monitor("out=%b", out); end endmodule [OK]

Hint: Start reset=1, delay 10, then reset=0, monitor output [OK]

Common Mistakes:

• Setting reset low initially instead of high
• Delaying reset assertion instead of deassertion
• Placing $monitor before reset release