Shift operators in Verilog - Step-by-Step Execution

Concept Flow - Shift operators

Start with input value

↓

Choose shift type

↓

Left shift

↓

Shift bits by N places

↓

Output shifted value

↓

End

The flow starts with an input value, chooses left or right shift, shifts bits by N places, and outputs the result.

Execution Sample

Verilog

reg [7:0] a = 8'b00011011;
reg [7:0] b;
b = a << 2;

This code shifts the bits of 'a' two places to the left and stores the result in 'b'.

Execution Table

Step	Variable	Value Before	Operation	Value After	Explanation
1	a	00011011	Initial value	00011011	Input value 'a' is set
2	b	--------	Assign b = a << 2	01101100	Bits shifted left by 2, zeros fill right
3	a	00011011	No change	00011011	'a' remains unchanged
4	b	01101100	Output	01101100	Final shifted value in 'b'

💡 Shift operation completes after moving bits left by 2 positions.

Variable Tracker

Variable	Start	After Shift	Final
a	00011011	00011011	00011011
b	--------	01101100	01101100

Key Moments - 2 Insights

Why does the value in 'b' have zeros on the right after left shift?

Because left shift moves bits to the left and fills empty right positions with zeros, as shown in execution_table step 2.

Does the original variable 'a' change after the shift operation?

No, 'a' stays the same because the shift result is assigned to 'b', as seen in execution_table step 3.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of 'b' after the shift operation?

A 11011000

B 01101100

C 00011011

D 00000000

💡 Hint

Check execution_table row 2 under 'Value After' for 'b'.

At which step does the variable 'a' remain unchanged?

A Step 1

B Step 2

C Step 3

D Step 4

💡 Hint

Look at execution_table step 3 where 'a' is noted as 'No change'.

If we change the shift from 'a << 2' to 'a >> 2', what would happen to the bits?

A Bits move right and zeros fill left

B Bits move left and zeros fill right

C Bits stay the same

D Bits reverse order

💡 Hint

Recall the concept_flow shows left shift moves bits left, right shift moves bits right.

Concept Snapshot

Shift operators move bits left or right.
Left shift (<<) moves bits left, fills right with zeros.
Right shift (>>) moves bits right, fills left with zeros.
Original value stays unchanged unless reassigned.
Used to multiply/divide by powers of two in hardware.

Full Transcript

This visual execution shows how shift operators work in Verilog. We start with an 8-bit value 'a' set to 00011011. When we do 'b = a << 2', the bits in 'a' move two places to the left, and zeros fill the empty spots on the right. The result 01101100 is stored in 'b'. The original 'a' remains unchanged. This process is shown step-by-step in the execution table and variable tracker. Key points include understanding that left shift fills zeros on the right and that the original variable does not change unless assigned. The quiz questions help reinforce these ideas by asking about values after shifts and effects of changing shift direction.

Practice

1. What does the left shift operator << do to a binary number in Verilog?

easy

A. Moves bits to the left, multiplying the number by powers of 2

B. Moves bits to the right, dividing the number by powers of 2

C. Reverses the bits in the number

D. Sets all bits to zero

Solution

1. Step 1: Understand the left shift operator

   The left shift operator << moves all bits in a binary number to the left by a specified number of positions.

2. Step 2: Effect on the number's value

   Moving bits left multiplies the number by 2 for each position shifted.

3. Final Answer:

   Moves bits to the left, multiplying the number by powers of 2 -> Option A

4. Quick Check:

   Left shift = multiply by 2 [OK]

Hint: Left shift multiplies by 2 powers quickly [OK]

Common Mistakes:

• Confusing left shift with right shift
• Thinking it reverses bits
• Assuming it clears bits

2. Which of the following is the correct syntax to shift a 4-bit register reg [3:0] a; two bits to the right in Verilog?

easy

A. a >>> 2;

B. a >> 2;

C. a << 2;

D. a >> 2 =;

Solution

1. Step 1: Identify the right shift operator syntax

   In Verilog, the right shift operator is >> and is used as variable >> number_of_bits;.

2. Step 2: Check the options for correct syntax

   a >> 2; uses a >> 2; which correctly shifts a two bits to the right. a << 2; is left shift, a >>> 2; is arithmetic right shift (signed), and a >> 2 =; has invalid syntax.

3. Final Answer:

   a >> 2; -> Option B

4. Quick Check:

   Right shift syntax = a >> number [OK]

Hint: Use >> for right shift, << for left shift [OK]

Common Mistakes:

• Using left shift operator instead of right shift
• Confusing logical and arithmetic shifts
• Writing invalid syntax like assignment inside shift

3. Given reg [7:0] x = 8'b00011010; what is the value of x << 3 in binary?

medium

A. 8'b11010000

B. 8'b11010000000

C. 8'b00011010

D. 8'b00000000

Solution

1. Step 1: Understand the initial value and shift

   The initial value is 00011010 (decimal 26). Left shifting by 3 moves bits 3 places left, adding zeros on the right.

2. Step 2: Perform the left shift

   Shifting left by 3: 00011010 becomes 11010000 (the leftmost bits shifted out are lost, and zeros fill from right).

3. Final Answer:

   8'b11010000 -> Option A

4. Quick Check:

   Left shift 3 bits = 11010000 [OK]

Hint: Left shift drops left bits, adds zeros right [OK]

Common Mistakes:

• Expecting longer bit width after shift
• Not losing bits shifted out
• Confusing left and right shift effects

4. What is wrong with this Verilog code snippet?

reg [3:0] a = 4'b1010;
reg [3:0] b;
b = a >> 5;

medium

A. Right shift operator should be << instead of >>

B. Syntax error due to missing semicolon

C. Shifting by more bits than width causes all zeros

D. Cannot assign shifted value to a register

Solution

1. Step 1: Analyze the shift amount vs register width

   The register a is 4 bits wide. Shifting right by 5 bits exceeds its width.

2. Step 2: Effect of shifting more than width

   Shifting more bits than the width results in all bits shifted out, so the result is zero.

3. Final Answer:

   Shifting by more bits than width causes all zeros -> Option C

4. Quick Check:

   Shift > width = zero result [OK]

Hint: Shift count > width clears all bits [OK]

Common Mistakes:

• Thinking syntax error occurs
• Confusing left and right shift operators
• Believing assignment to register is invalid

5. You want to multiply a 6-bit unsigned number num by 8 using shift operators in Verilog. Which expression correctly does this without overflow?

hard

A. num >>> 3

B. num >> 3

C. num << 2

D. num << 3

Solution

1. Step 1: Understand multiplication by powers of 2 using shifts

   Multiplying by 8 equals multiplying by 2^3, so shifting left by 3 bits achieves this.

2. Step 2: Check for overflow considerations

   Since num is 6 bits, shifting left by 3 bits results in a 9-bit value. To avoid overflow, the result should be stored in a wider register. The expression num << 3 correctly multiplies by 8.

3. Final Answer:

   num << 3 -> Option D

4. Quick Check:

   Multiply by 8 = shift left 3 [OK]

Hint: Multiply by 8 = shift left 3 bits [OK]

Common Mistakes:

• Using right shift instead of left shift
• Using arithmetic right shift (>>>)
• Shifting by wrong number of bits