Shift operators in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this left shift operation?

Consider the following Verilog code snippet. What is the value of result after the shift operation?

Verilog

module test;
  reg [7:0] a = 8'b0001_0011; // decimal 19
  reg [7:0] result;
  initial begin
    result = a << 2;
  end
endmodule

A 8'b0011_0000

B 8'b1001_1000

C 8'b0000_0110

D 8'b0100_1100

💡 Hint

Left shift moves bits to the left and fills with zeros on the right.

The original value is 00010011 (decimal 19). Shifting left by 2 moves bits two places left: 01001100 (decimal 76).

❓ Predict Output

intermediate

What is the output of this right shift operation?

Given the Verilog code below, what is the value of result after the right shift?

Verilog

module test;
  reg [7:0] a = 8'b1100_1000; // decimal 200
  reg [7:0] result;
  initial begin
    result = a >> 3;
  end
endmodule

A 8'b0001_1001

B 8'b0000_1100

C 8'b1111_1001

D 8'b0001_1000

💡 Hint

Right shift moves bits to the right and fills with zeros on the left for unsigned values.

Original value 11001000 (200 decimal). Shifting right by 3 bits gives 00011001 (25 decimal).

❓ Predict Output

advanced

What is the output of this arithmetic right shift on a signed value?

In Verilog, consider this signed 8-bit value and the arithmetic right shift operation. What is the value of result?

Verilog

module test;
  reg signed [7:0] a = -8'sd16; // binary 1111_0000
  reg signed [7:0] result;
  initial begin
    result = a >>> 2;
  end
endmodule

A 8'b1111_1100

B 8'b0011_1100

C 8'b1111_0011

D 8'b0000_0100

💡 Hint

Arithmetic right shift preserves the sign bit (leftmost bit).

The value -16 in 8-bit signed is 11110000. Arithmetic right shift by 2 keeps sign bits: 11111100 (-4 decimal).

❓ Predict Output

advanced

What is the result of this shift with a variable shift amount?

Given the Verilog code below, what is the value of result after shifting?

Verilog

module test;
  reg [7:0] a = 8'b0001_1111; // decimal 31
  reg [2:0] shift_amt = 3'd4;
  reg [7:0] result;
  initial begin
    result = a << shift_amt;
  end
endmodule

A 8'b1111_0000_0000

B 8'b1111_0000

C 8'b0001_1111

D 8'b1111_0000_0000_0000

💡 Hint

Shifting left by 4 moves bits 4 places left, filling with zeros on the right.

31 decimal is 00011111. Shift left by 4 gives 11110000 (decimal 240).

🧠 Conceptual

expert

How many bits are set to 1 after this combined shift operation?

Consider this Verilog code snippet. How many bits in result are set to 1 after execution?

Verilog

module test;
  reg [7:0] a = 8'b1010_1010;
  reg [7:0] result;
  initial begin
    result = (a << 1) >> 2;
  end
endmodule

A 5

B 4

C 3

D 2

💡 Hint

Perform the shifts step-by-step and count the 1 bits in the final result.

a = 10101010. Left shift by 1: 01010100. Right shift by 2: 00010101. Counting 1 bits: 3 bits set.

Practice

1. What does the left shift operator << do to a binary number in Verilog?

easy

A. Moves bits to the left, multiplying the number by powers of 2

B. Moves bits to the right, dividing the number by powers of 2

C. Reverses the bits in the number

D. Sets all bits to zero

Solution

1. Step 1: Understand the left shift operator

   The left shift operator << moves all bits in a binary number to the left by a specified number of positions.

2. Step 2: Effect on the number's value

   Moving bits left multiplies the number by 2 for each position shifted.

3. Final Answer:

   Moves bits to the left, multiplying the number by powers of 2 -> Option A

4. Quick Check:

   Left shift = multiply by 2 [OK]

Hint: Left shift multiplies by 2 powers quickly [OK]

Common Mistakes:

• Confusing left shift with right shift
• Thinking it reverses bits
• Assuming it clears bits

2. Which of the following is the correct syntax to shift a 4-bit register reg [3:0] a; two bits to the right in Verilog?

easy

A. a >>> 2;

B. a >> 2;

C. a << 2;

D. a >> 2 =;

Solution

1. Step 1: Identify the right shift operator syntax

   In Verilog, the right shift operator is >> and is used as variable >> number_of_bits;.

2. Step 2: Check the options for correct syntax

   a >> 2; uses a >> 2; which correctly shifts a two bits to the right. a << 2; is left shift, a >>> 2; is arithmetic right shift (signed), and a >> 2 =; has invalid syntax.

3. Final Answer:

   a >> 2; -> Option B

4. Quick Check:

   Right shift syntax = a >> number [OK]

Hint: Use >> for right shift, << for left shift [OK]

Common Mistakes:

• Using left shift operator instead of right shift
• Confusing logical and arithmetic shifts
• Writing invalid syntax like assignment inside shift

3. Given reg [7:0] x = 8'b00011010; what is the value of x << 3 in binary?

medium

A. 8'b11010000

B. 8'b11010000000

C. 8'b00011010

D. 8'b00000000

Solution

1. Step 1: Understand the initial value and shift

   The initial value is 00011010 (decimal 26). Left shifting by 3 moves bits 3 places left, adding zeros on the right.

2. Step 2: Perform the left shift

   Shifting left by 3: 00011010 becomes 11010000 (the leftmost bits shifted out are lost, and zeros fill from right).

3. Final Answer:

   8'b11010000 -> Option A

4. Quick Check:

   Left shift 3 bits = 11010000 [OK]

Hint: Left shift drops left bits, adds zeros right [OK]

Common Mistakes:

• Expecting longer bit width after shift
• Not losing bits shifted out
• Confusing left and right shift effects

4. What is wrong with this Verilog code snippet?

reg [3:0] a = 4'b1010;
reg [3:0] b;
b = a >> 5;

medium

A. Right shift operator should be << instead of >>

B. Syntax error due to missing semicolon

C. Shifting by more bits than width causes all zeros

D. Cannot assign shifted value to a register

Solution

1. Step 1: Analyze the shift amount vs register width

   The register a is 4 bits wide. Shifting right by 5 bits exceeds its width.

2. Step 2: Effect of shifting more than width

   Shifting more bits than the width results in all bits shifted out, so the result is zero.

3. Final Answer:

   Shifting by more bits than width causes all zeros -> Option C

4. Quick Check:

   Shift > width = zero result [OK]

Hint: Shift count > width clears all bits [OK]

Common Mistakes:

• Thinking syntax error occurs
• Confusing left and right shift operators
• Believing assignment to register is invalid

5. You want to multiply a 6-bit unsigned number num by 8 using shift operators in Verilog. Which expression correctly does this without overflow?

hard

A. num >>> 3

B. num >> 3

C. num << 2

D. num << 3

Solution

1. Step 1: Understand multiplication by powers of 2 using shifts

   Multiplying by 8 equals multiplying by 2^3, so shifting left by 3 bits achieves this.

2. Step 2: Check for overflow considerations

   Since num is 6 bits, shifting left by 3 bits results in a 9-bit value. To avoid overflow, the result should be stored in a wider register. The expression num << 3 correctly multiplies by 8.

3. Final Answer:

   num << 3 -> Option D

4. Quick Check:

   Multiply by 8 = shift left 3 [OK]

Hint: Multiply by 8 = shift left 3 bits [OK]

Common Mistakes:

• Using right shift instead of left shift
• Using arithmetic right shift (>>>)
• Shifting by wrong number of bits