Reduction operators in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of reduction AND operator

What is the output of the following Verilog code snippet?

module test;
  reg [3:0] a = 4'b1101;
  wire out;
  assign out = &a;
  initial begin
    $display("out = %b", out);
  end
endmodule

Verilog

module test;
  reg [3:0] a = 4'b1101;
  wire out;
  assign out = &a;
  initial begin
    $display("out = %b", out);
  end
endmodule

A out = 0

B out = 1

C out = 4'b1101

D out = 4'b1111

💡 Hint

The reduction AND operator returns 1 only if all bits are 1.

The input 'a' is 1101. Since not all bits are 1 (the second bit is 0), the reduction AND (&a) outputs 0.

❓ Predict Output

intermediate

Output of reduction OR operator

What will be printed by this Verilog code?

module test;
  reg [3:0] b = 4'b0000;
  wire out;
  assign out = |b;
  initial begin
    $display("out = %b", out);
  end
endmodule

Verilog

module test;
  reg [3:0] b = 4'b0000;
  wire out;
  assign out = |b;
  initial begin
    $display("out = %b", out);
  end
endmodule

A out = 4'b0000

B out = 1

C out = 0

D out = 4'b1111

💡 Hint

The reduction OR operator returns 1 if any bit is 1.

Since all bits in b are 0, the reduction OR (|b) outputs 0.

❓ Predict Output

advanced

Output of reduction XOR operator

What is the output of this Verilog code?

module test;
  reg [3:0] c = 4'b1011;
  wire out;
  assign out = ^c;
  initial begin
    $display("out = %b", out);
  end
endmodule

Verilog

module test;
  reg [3:0] c = 4'b1011;
  wire out;
  assign out = ^c;
  initial begin
    $display("out = %b", out);
  end
endmodule

A out = 4'b1011

B out = 1

C out = 0

D out = 4'b0100

💡 Hint

The reduction XOR operator returns 1 if the number of 1 bits is odd.

The bits in c are 1,0,1,1 which has three 1s (odd count), so ^c outputs 1.

❓ Predict Output

advanced

Value of variable after reduction NAND operator

What value does 'out' hold after this code runs?

module test;
  reg [3:0] d = 4'b1111;
  wire out;
  assign out = ~&d;
  initial begin
    $display("out = %b", out);
  end
endmodule

Verilog

module test;
  reg [3:0] d = 4'b1111;
  wire out;
  assign out = ~&d;
  initial begin
    $display("out = %b", out);
  end
endmodule

A out = 4'b0000

B out = 4'b1111

C out = 0

D out = 1

💡 Hint

NAND is the negation of AND.

Since &d is 1 (all bits 1), ~&d is 0.

🧠 Conceptual

expert

Understanding reduction NOR operator behavior

Given the Verilog code below, what is the output?

module test;
  reg [3:0] e = 4'b0001;
  wire out;
  assign out = ~|e;
  initial begin
    $display("out = %b", out);
  end
endmodule

Verilog

module test;
  reg [3:0] e = 4'b0001;
  wire out;
  assign out = ~|e;
  initial begin
    $display("out = %b", out);
  end
endmodule

A out = 0

B out = 1

C out = 4'b0000

D out = 4'b1111

💡 Hint

Reduction NOR is the negation of reduction OR.

Since |e is 1 (because one bit is 1), ~|e is 0.

Practice

1. What does the Verilog reduction operator & do when applied to a multi-bit signal?

easy

A. It XORs all bits together to produce a single bit result.

B. It ORs all bits together to produce a single bit result.

C. It ANDs all bits together to produce a single bit result.

D. It inverts all bits of the signal.

Solution

1. Step 1: Understand the & reduction operator

   The & operator in Verilog combines all bits of a signal by ANDing them together.

2. Step 2: Result of & operator

   If all bits are 1, the result is 1; otherwise, it is 0.

3. Final Answer:

   It ANDs all bits together to produce a single bit result. -> Option C

4. Quick Check:

   Reduction AND = AND all bits [OK]

Hint: AND reduction means all bits must be 1 for output 1 [OK]

Common Mistakes:

• Confusing & with | or ^ operators
• Thinking it inverts bits instead of combining
• Assuming it returns multi-bit result

2. Which of the following is the correct syntax to apply a reduction OR operator on a 4-bit signal data[3:0] in Verilog?

easy

A. result = &data;

B. result = |data;

C. result = data|4;

D. result = data|;

Solution

1. Step 1: Identify reduction OR syntax

   The reduction OR operator uses the pipe symbol before the signal: |signal.

2. Step 2: Check each option

   result = |data; correctly places | before data. Others have syntax errors or wrong operators.

3. Final Answer:

   result = |data; -> Option B

4. Quick Check:

   Reduction OR syntax = |signal [OK]

Hint: Put | before signal name for reduction OR [OK]

Common Mistakes:

• Placing | after the signal
• Adding extra numbers or symbols
• Using & instead of |

3. Given wire [3:0] a = 4'b1011; and wire result = ^a;, what is the value of result?

medium

A. 1

B. 0

C. 4'b1011

D. Syntax error

Solution

1. Step 1: Understand ^ reduction operator

   The ^ operator XORs all bits of the signal together.

2. Step 2: Calculate XOR of bits in 1011

   Bits: 1 ^ 0 = 1, 1 ^ 1 = 0, 0 ^ 1 = 1. Final XOR is 1 ^ 0 ^ 1 ^ 1 = 1.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   Reduction XOR of 1011 = 1 [OK]

Hint: XOR bits one by one for reduction XOR [OK]

Common Mistakes:

• Confusing XOR with OR or AND
• Returning multi-bit instead of single bit
• Miscomputing XOR of bits

4. Identify the error in this Verilog code snippet:

wire [3:0] b = 4'b1100;
wire c = &b;
wire d = b&;

medium

A. The line wire d = b&; has incorrect reduction operator syntax.

B. The line wire c = &b; is invalid syntax.

C. The signal b must be declared as reg, not wire.

D. There is no error in the code.

Solution

1. Step 1: Check reduction operator syntax

   Reduction operators must be placed before the signal, e.g., &b.

2. Step 2: Identify incorrect line

   The line wire d = b&; places & after b, which is invalid syntax.

3. Final Answer:

   The line wire d = b&; has incorrect reduction operator syntax. -> Option A

4. Quick Check:

   Reduction operator must precede signal [OK]

Hint: Reduction operator always before signal name [OK]

Common Mistakes:

• Placing operator after signal
• Confusing wire and reg for this context
• Assuming no syntax error

5. You want to check if all bits of an 8-bit signal data[7:0] are zero using reduction operators. Which expression correctly returns 1 if all bits are zero, else 0?

hard

A. result = &data;

B. result = ~&data;

C. result = |data;

D. result = ~|data;

Solution

1. Step 1: Understand the goal

   We want 1 if all bits are zero, else 0.

2. Step 2: Use reduction OR and NOT

   Reduction OR |data is 1 if any bit is 1. Negating it with ~ gives 1 only if all bits are zero.

3. Final Answer:

   result = ~|data; -> Option D

4. Quick Check:

   All zero check = NOT OR reduction [OK]

Hint: Use ~| to check all bits zero quickly [OK]

Common Mistakes:

• Using &data which checks all ones, not zeros
• Using |data without negation
• Using ~&data which checks all ones inverted