Module as the basic building block in Verilog - Step-by-Step Execution

Concept Flow - Module as the basic building block

Define module with name

↓

Declare inputs and outputs

↓

Describe internal logic

↓

End module

↓

Use module in design

A module is defined with inputs and outputs, contains internal logic, and ends with 'endmodule'. It is the basic unit used to build larger designs.

Execution Sample

Verilog

module and_gate(input a, input b, output y);
  assign y = a & b;
endmodule

Defines a simple AND gate module with two inputs and one output.

Execution Table

Step	Action	Code Line	Result
1	Start module definition	module and_gate(input a, input b, output y);	Module named 'and_gate' created with inputs a,b and output y
2	Define output logic	assign y = a & b;	Output y is assigned the AND of inputs a and b
3	End module	endmodule	Module definition ends
4	Module ready to be instantiated	N/A	Module can be used in other designs

💡 Module definition completed and ready for use in design

Variable Tracker

Variable	Start	After Step 2	Final
a	input	input	input
b	input	input	input
y	output undefined	a & b	a & b

Key Moments - 3 Insights

Why do we use 'assign' inside a module?

'assign' is used to continuously drive the output based on inputs, as shown in step 2 of the execution table where y is assigned a & b.

What marks the end of a module?

The keyword 'endmodule' marks the end, as shown in step 3 of the execution table.

Can a module be used before it is fully defined?

No, the module must be fully defined and ended with 'endmodule' before it can be instantiated, as noted in step 4.

Visual Quiz - 3 Questions

Look at the execution table, what happens at step 2?

A Module starts definition

B Module ends

C Output y is assigned the AND of inputs a and b

D Module is instantiated

💡 Hint

Refer to the 'Action' and 'Result' columns in row 2 of the execution table.

At which step does the module definition end?

A Step 3

B Step 2

C Step 1

D Step 4

💡 Hint

Look for the 'endmodule' keyword in the 'Code Line' column.

If we remove 'assign' from step 2, what changes in the variable_tracker?

A Output y becomes input

B Output y remains undefined

C Inputs a and b change values

D No change

💡 Hint

Check how y is assigned in the variable_tracker after step 2.

Concept Snapshot

module <name>(input/output declarations);
  // internal logic
  assign output = expression;
endmodule

- Modules group logic
- Inputs and outputs declared
- 'assign' drives outputs
- Ends with 'endmodule'

Full Transcript

In Verilog, a module is the basic building block of hardware design. We start by defining a module with a name and declare its inputs and outputs. Inside the module, we describe the logic, often using 'assign' statements to connect outputs to expressions of inputs. The module ends with the 'endmodule' keyword. This module can then be used in larger designs by instantiating it. The execution table shows the step-by-step process of defining a simple AND gate module. Variables a and b are inputs, and y is the output assigned as the AND of a and b. Key moments clarify why 'assign' is used, the importance of 'endmodule', and when a module can be used. The visual quiz tests understanding of these steps and their effects on variables.

Practice

1.

What is the main purpose of a module in Verilog?

easy

A. It defines a reusable block of hardware design.

B. It runs software programs inside the chip.

C. It stores data permanently like a hard drive.

D. It controls the power supply of the circuit.

Solution

1. Step 1: Understand what a module represents

   A module in Verilog is a block that describes hardware behavior or structure.

2. Step 2: Identify the purpose of modules

   Modules help organize and reuse hardware design parts, not software or power control.

3. Final Answer:

   It defines a reusable block of hardware design. -> Option A

4. Quick Check:

   Module = reusable hardware block [OK]

Hint: Modules are like building blocks for hardware [OK]

Common Mistakes:

• Thinking modules run software code
• Confusing modules with memory storage
• Assuming modules control power

2.

Which of the following is the correct way to start and end a Verilog module named my_module?

?

easy

A. start my_module; finish

B. module my_module(); endmodule

C. begin my_module() end

D. module: my_module() endmodule:

Solution

1. Step 1: Recall Verilog module syntax

   A module starts with the keyword module followed by the module name and ends with endmodule.

2. Step 2: Check each option

   module my_module(); endmodule uses correct keywords and syntax. Others use invalid keywords or punctuation.

3. Final Answer:

   module my_module(); endmodule -> Option B

4. Quick Check:

   module ... endmodule = correct syntax [OK]

Hint: Modules always start with 'module' and end with 'endmodule' [OK]

Common Mistakes:

• Using wrong keywords like start or finish
• Missing parentheses after module name
• Adding colons or semicolons incorrectly

3.

What will be the output of the following Verilog module when input_a = 1 and input_b = 0?

module simple_and(input input_a, input input_b, output reg out);
  always @(*) begin
    out = input_a & input_b;
  end
endmodule

medium

A. out = input_b

B. out = 1

C. out = input_a

D. out = 0

Solution

1. Step 1: Understand the operation inside the module

   The module assigns out as the AND of input_a and input_b.

2. Step 2: Calculate the AND of inputs

   Given input_a = 1 and input_b = 0, 1 & 0 = 0.

3. Final Answer:

   out = 0 -> Option D

4. Quick Check:

   1 AND 0 = 0 [OK]

Hint: AND output is 1 only if both inputs are 1 [OK]

Common Mistakes:

• Assuming output equals one input directly
• Confusing AND with OR operation
• Ignoring that output is reg type

4.

Identify the error in this Verilog module code:

module faulty_module(input a, input b, output reg c);
  always @(*) begin
    c = a | b
  end
endmodule

medium

A. Wrong sensitivity list in always block.

B. Incorrect use of 'reg' for output.

C. Missing semicolon after assignment inside always block.

D. Module name should be capitalized.

Solution

1. Step 1: Check syntax inside always block

   The assignment c = a | b is missing a semicolon at the end.

2. Step 2: Verify other parts

   Using reg for output is correct; sensitivity list @(*) is valid; module names can be lowercase.

3. Final Answer:

   Missing semicolon after assignment inside always block. -> Option C

4. Quick Check:

   Statements inside always need semicolons [OK]

Hint: Always end statements inside always block with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after assignment
• Thinking output cannot be reg
• Believing sensitivity list must list signals explicitly

5.

You want to create a Verilog module named counter that counts from 0 to 3 repeatedly using a 2-bit output count. Which module header and port declaration is correct?

hard

A. module counter(input clk, output reg [1:0] count); endmodule

B. module counter(output reg [2:0] count, input clk); endmodule

C. module counter(input clk, output [1:0] count); endmodule

D. module counter(input clk, output reg count[1:0]); endmodule

Solution

1. Step 1: Identify correct port order and types

   The clock input clk should be input, and count is a 2-bit register output, declared as output reg [1:0] count.

2. Step 2: Check each option

   module counter(input clk, output reg [1:0] count); endmodule correctly declares ports and types. module counter(output reg [2:0] count, input clk); endmodule has wrong bit width. module counter(input clk, output [1:0] count); endmodule misses reg for output assigned inside always block. module counter(input clk, output reg count[1:0]); endmodule uses incorrect syntax for bus declaration.

3. Final Answer:

   module counter(input clk, output reg [1:0] count); endmodule -> Option A

4. Quick Check:

   Output reg [1:0] count with input clk = correct [OK]

Hint: Use 'output reg [bits]' for outputs assigned in always blocks [OK]

Common Mistakes:

• Forgetting 'reg' for output assigned in always block
• Incorrect bus declaration syntax
• Swapping input and output order