Module as the basic building block in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple module instantiation

What is the output of this Verilog testbench when simulating the module and_gate?

Verilog

module and_gate(input a, input b, output y);
  assign y = a & b;
endmodule

module test;
  reg a, b;
  wire y;
  and_gate uut(.a(a), .b(b), .y(y));

  initial begin
    a = 1'b0; b = 1'b0;
    #10;
    $display("Output: %b", y);
    a = 1'b1; b = 1'b0;
    #10;
    $display("Output: %b", y);
    a = 1'b1; b = 1'b1;
    #10;
    $display("Output: %b", y);
  end
endmodule

A

Output: 0
Output: 0
Output: 1

B

Output: 0
Output: 1
Output: 1

C

Output: 1
Output: 0
Output: 1

D

Output: 0
Output: 0
Output: 0

💡 Hint

Remember that AND gate output is 1 only when both inputs are 1.

The AND gate outputs 1 only when both inputs are 1. For inputs (0,0) and (1,0), output is 0. For (1,1), output is 1.

🧠 Conceptual

intermediate

Understanding module ports and connections

Which statement correctly describes the role of ports in a Verilog module?

A Ports automatically generate clock signals inside the module.

B Ports are used only to declare internal signals inside a module.

C Ports define the interface of a module, specifying inputs and outputs for communication.

D Ports are used to store values permanently inside the module.

💡 Hint

Think about how modules connect to each other.

Ports are the input and output points of a module, allowing it to communicate with other modules or testbenches.

🔧 Debug

advanced

Identify the error in module instantiation

What error will occur when compiling this Verilog code?

Verilog

module inverter(input a, output y);
  assign y = ~a;
endmodule

module test;
  reg a;
  wire y;
  inverter uut(a, y);

  initial begin
    a = 1'b0;
    #5;
    $display("Inverted: %b", y);
  end
endmodule

A No error, code compiles and runs correctly.

B Syntax error due to missing port names in module instantiation.

C Type error because 'a' is reg and 'y' is wire.

D Runtime error because output 'y' is not driven.

💡 Hint

Check if positional port connections are allowed.

Positional port connections without names are allowed if the order matches the module definition. 'reg' and 'wire' types are correctly used here.

❓ Predict Output

advanced

Output of nested module instantiation

What is the output of this Verilog testbench?

Verilog

module or_gate(input a, input b, output y);
  assign y = a | b;
endmodule

module top_module(input x, input z, output out);
  wire w;
  or_gate u1(.a(x), .b(z), .y(w));
  or_gate u2(.a(w), .b(z), .y(out));
endmodule

module test;
  reg x, z;
  wire out;
  top_module uut(.x(x), .z(z), .out(out));

  initial begin
    x = 1'b0; z = 1'b0; #5 $display("Output: %b", out);
    x = 1'b1; z = 1'b0; #5 $display("Output: %b", out);
    x = 1'b0; z = 1'b1; #5 $display("Output: %b", out);
    x = 1'b1; z = 1'b1; #5 $display("Output: %b", out);
  end
endmodule

A

Output: 1
Output: 1
Output: 1
Output: 1

B

Output: 0
Output: 0
Output: 1
Output: 1

C

Output: 0
Output: 1
Output: 0
Output: 1

D

Output: 0
Output: 1
Output: 1
Output: 1

💡 Hint

Remember OR gate outputs 1 if any input is 1.

The first OR gate outputs 1 if x or z is 1. The second OR gate outputs 1 if w or z is 1. The outputs correspond to the OR logic applied twice.

🧠 Conceptual

expert

Role of modules in hierarchical design

Which statement best describes the role of modules in Verilog hierarchical design?

A Modules automatically optimize hardware without user intervention.

B Modules allow building complex designs by combining smaller reusable blocks with defined interfaces.

C Modules replace the need for wires and registers in a design.

D Modules are only used for testbenches and cannot be nested.

💡 Hint

Think about how big circuits are built from smaller parts.

Modules are the basic building blocks that can be combined and reused to create complex hardware designs with clear interfaces.

Practice

1.

What is the main purpose of a module in Verilog?

easy

A. It defines a reusable block of hardware design.

B. It runs software programs inside the chip.

C. It stores data permanently like a hard drive.

D. It controls the power supply of the circuit.

Solution

1. Step 1: Understand what a module represents

   A module in Verilog is a block that describes hardware behavior or structure.

2. Step 2: Identify the purpose of modules

   Modules help organize and reuse hardware design parts, not software or power control.

3. Final Answer:

   It defines a reusable block of hardware design. -> Option A

4. Quick Check:

   Module = reusable hardware block [OK]

Hint: Modules are like building blocks for hardware [OK]

Common Mistakes:

• Thinking modules run software code
• Confusing modules with memory storage
• Assuming modules control power

2.

Which of the following is the correct way to start and end a Verilog module named my_module?

?

easy

A. start my_module; finish

B. module my_module(); endmodule

C. begin my_module() end

D. module: my_module() endmodule:

Solution

1. Step 1: Recall Verilog module syntax

   A module starts with the keyword module followed by the module name and ends with endmodule.

2. Step 2: Check each option

   module my_module(); endmodule uses correct keywords and syntax. Others use invalid keywords or punctuation.

3. Final Answer:

   module my_module(); endmodule -> Option B

4. Quick Check:

   module ... endmodule = correct syntax [OK]

Hint: Modules always start with 'module' and end with 'endmodule' [OK]

Common Mistakes:

• Using wrong keywords like start or finish
• Missing parentheses after module name
• Adding colons or semicolons incorrectly

3.

What will be the output of the following Verilog module when input_a = 1 and input_b = 0?

module simple_and(input input_a, input input_b, output reg out);
  always @(*) begin
    out = input_a & input_b;
  end
endmodule

medium

A. out = input_b

B. out = 1

C. out = input_a

D. out = 0

Solution

1. Step 1: Understand the operation inside the module

   The module assigns out as the AND of input_a and input_b.

2. Step 2: Calculate the AND of inputs

   Given input_a = 1 and input_b = 0, 1 & 0 = 0.

3. Final Answer:

   out = 0 -> Option D

4. Quick Check:

   1 AND 0 = 0 [OK]

Hint: AND output is 1 only if both inputs are 1 [OK]

Common Mistakes:

• Assuming output equals one input directly
• Confusing AND with OR operation
• Ignoring that output is reg type

4.

Identify the error in this Verilog module code:

module faulty_module(input a, input b, output reg c);
  always @(*) begin
    c = a | b
  end
endmodule

medium

A. Wrong sensitivity list in always block.

B. Incorrect use of 'reg' for output.

C. Missing semicolon after assignment inside always block.

D. Module name should be capitalized.

Solution

1. Step 1: Check syntax inside always block

   The assignment c = a | b is missing a semicolon at the end.

2. Step 2: Verify other parts

   Using reg for output is correct; sensitivity list @(*) is valid; module names can be lowercase.

3. Final Answer:

   Missing semicolon after assignment inside always block. -> Option C

4. Quick Check:

   Statements inside always need semicolons [OK]

Hint: Always end statements inside always block with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after assignment
• Thinking output cannot be reg
• Believing sensitivity list must list signals explicitly

5.

You want to create a Verilog module named counter that counts from 0 to 3 repeatedly using a 2-bit output count. Which module header and port declaration is correct?

hard

A. module counter(input clk, output reg [1:0] count); endmodule

B. module counter(output reg [2:0] count, input clk); endmodule

C. module counter(input clk, output [1:0] count); endmodule

D. module counter(input clk, output reg count[1:0]); endmodule

Solution

1. Step 1: Identify correct port order and types

   The clock input clk should be input, and count is a 2-bit register output, declared as output reg [1:0] count.

2. Step 2: Check each option

   module counter(input clk, output reg [1:0] count); endmodule correctly declares ports and types. module counter(output reg [2:0] count, input clk); endmodule has wrong bit width. module counter(input clk, output [1:0] count); endmodule misses reg for output assigned inside always block. module counter(input clk, output reg count[1:0]); endmodule uses incorrect syntax for bus declaration.

3. Final Answer:

   module counter(input clk, output reg [1:0] count); endmodule -> Option A

4. Quick Check:

   Output reg [1:0] count with input clk = correct [OK]

Hint: Use 'output reg [bits]' for outputs assigned in always blocks [OK]

Common Mistakes:

• Forgetting 'reg' for output assigned in always block
• Incorrect bus declaration syntax
• Swapping input and output order