How Verilog maps to physical gates - Try It Yourself

How Verilog Maps to Physical Gates

📖 Scenario: You are designing a simple digital circuit using Verilog. This circuit will be synthesized into physical gates on a chip. Understanding how your Verilog code translates to gates helps you design efficient hardware.

🎯 Goal: Build a simple Verilog module for a 2-input AND gate, then extend it to a 2-input OR gate, and finally combine them to create a small circuit. Observe how these Verilog statements correspond to physical gates.

📋 What You'll Learn

Create a Verilog module named and_gate with inputs a and b and output y implementing an AND gate.

Create a Verilog module named or_gate with inputs a and b and output y implementing an OR gate.

Create a Verilog module named and_or_circuit that uses instances of and_gate and or_gate to combine signals.

Print the Verilog code for the final combined module.

💡 Why This Matters

🌍 Real World

Digital designers write Verilog code to describe circuits. This code is then turned into physical gates on chips used in computers, phones, and other electronics.

💼 Career

Understanding how Verilog maps to gates is essential for hardware engineers, FPGA developers, and anyone working in chip design or embedded systems.

1

Create a 2-input AND gate module

Write a Verilog module named and_gate with inputs a and b and output y. Use an assign statement to set y as the AND of a and b.

Verilog

// Your code here

Hint

Use assign y = a & b; inside the module to create the AND logic.

2

Create a 2-input OR gate module

Add a Verilog module named or_gate with inputs a and b and output y. Use an assign statement to set y as the OR of a and b.

Verilog

module and_gate(input a, input b, output y);
    assign y = a & b;
endmodule

// Your code here

Hint

Use assign y = a | b; inside the or_gate module.

3

Combine AND and OR gates in a new module

Create a Verilog module named and_or_circuit with inputs x, y, and z, and output out. Instantiate and_gate as and1 with inputs x and y. Instantiate or_gate as or1 with inputs and1's output and z. Connect or1's output to out.

Verilog

module and_gate(input a, input b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, input b, output y);
    assign y = a | b;
endmodule

// Your code here

Hint

Use wires to connect outputs of one module to inputs of another.

4

Display the final combined Verilog code

Print the entire Verilog code for the and_or_circuit module including the and_gate and or_gate modules.

Verilog

module and_gate(input a, input b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, input b, output y);
    assign y = a | b;
endmodule

module and_or_circuit(input x, input y, input z, output out);
    wire and_out;
    and_gate and1(.a(x), .b(y), .y(and_out));
    or_gate or1(.a(and_out), .b(z), .y(out));
endmodule

// Your code here

Hint

Use $display statements to print each line of the Verilog code.

Practice

1. Which Verilog construct directly represents a physical AND gate in hardware?

easy

A. reg out; out = ~a;

B. assign out = a & b;

C. wire out = a ^ b;

D. always @(posedge clk) out <= a | b;

Solution

1. Step 1: Identify the logic operation in each statement

   assign out = a & b; uses bitwise AND (&), which maps to an AND gate. always @(posedge clk) out <= a | b; uses OR (|) but inside an always block with clock, so it implies sequential logic, not a simple AND gate. wire out = a ^ b; uses XOR (^), which maps to XOR gate. reg out; out = ~a; uses NOT (~), which maps to NOT gate.

2. Step 2: Match the operation to the physical gate

   The AND operation in assign out = a & b; directly corresponds to a physical AND gate in hardware.

3. Final Answer:

   assign out = a & b; -> Option B

4. Quick Check:

   AND operation = assign out = a & b; [OK]

Hint: Bitwise & in assign maps to AND gate [OK]

Common Mistakes:

• Confusing sequential always block with combinational gate
• Mixing bitwise and logical operators
• Assuming reg implies a gate directly

2. Which of the following is the correct Verilog syntax to instantiate a 2-input NAND gate named nand1?

easy

A. nand (out, in1, in2) nand1;

B. and nand1 (out, in1, in2);

C. nand1 nand (out, in1, in2);

D. nand nand1 (out, in1, in2);

Solution

1. Step 1: Recall the gate instantiation syntax in Verilog

   The syntax is: gate_type instance_name (output, input1, input2, ...);

2. Step 2: Match the syntax to the options

   nand nand1 (out, in1, in2); matches the correct syntax with gate type nand, instance name nand1, and ports in correct order. Other options have incorrect order or wrong keywords.

3. Final Answer:

   nand nand1 (out, in1, in2); -> Option D

4. Quick Check:

   Gate instantiation = nand nand1 (out, in1, in2); [OK]

Hint: Gate type first, then instance name, then ports [OK]

Common Mistakes:

• Swapping instance name and gate type
• Incorrect port order
• Using invalid syntax like missing semicolon

3. Given the Verilog code:

assign y = ~(a & b) | c;

What is the equivalent logic gate expression for output y?

medium

A. y = (a NAND b) OR c

B. y = (a AND b) NOR c

C. y = (a OR b) NAND c

D. y = (a NOR b) AND c

Solution

1. Step 1: Analyze the expression ~(a & b) | c

   The expression first computes a & b, then negates it (~), which is NAND operation. Then it ORs the result with c.

2. Step 2: Translate to gate-level expression

   This matches (a NAND b) OR c exactly.

3. Final Answer:

   y = (a NAND b) OR c -> Option A

4. Quick Check:

   ~(a & b) = NAND, then OR with c = y = (a NAND b) OR c [OK]

Hint: ~(a & b) means NAND of a and b [OK]

Common Mistakes:

• Confusing NOR with NAND
• Misreading operator precedence
• Ignoring the negation on AND

4. Identify the error in this Verilog code snippet that tries to implement a 2-input OR gate:

module or_gate(output y, input a, b);
  wire y;
  assign y = a | b;
endmodule

medium

A. Using assign inside module is not allowed

B. Missing semicolon after assign statement

C. Declaring output y as wire inside the module causes conflict

D. Input ports a and b must be declared as reg

Solution

1. Step 1: Check port and internal signal declarations

   The output y is declared as a port and then redeclared as a wire inside the module, which causes a conflict.

2. Step 2: Understand Verilog rules for output ports

   Output ports default to wire type; redeclaring them as wire inside the module is redundant and causes error.

3. Final Answer:

   Declaring output y as wire inside the module causes conflict -> Option C

4. Quick Check:

   Output redeclaration error = Declaring output y as wire inside the module causes conflict [OK]

Hint: Don't redeclare output ports as wire inside module [OK]

Common Mistakes:

• Thinking assign needs semicolon error
• Believing inputs must be reg
• Assuming assign is disallowed inside modules

5. You want to implement a 3-input majority gate in Verilog that outputs 1 if at least two inputs are 1. Which of the following Verilog expressions correctly maps to the minimal physical gate implementation?

hard

A. assign y = (a & b) | (b & c) | (a & c);

B. assign y = (a | b) & (b | c) & (a | c);

C. assign y = (a & b & c) | (~a & b & c) | (a & ~b & c) | (a & b & ~c);

D. assign y = (a ^ b) & (b ^ c) & (a ^ c);

Solution

1. Step 1: Understand majority gate logic

   A 3-input majority gate outputs 1 if at least two inputs are 1. This is equivalent to the OR of all pairs ANDed together.

2. Step 2: Analyze each expression

   assign y = (a & b) | (b & c) | (a & c); uses OR of all pairs ANDed: (a & b) | (b & c) | (a & c), which is minimal and correct. assign y = (a | b) & (b | c) & (a | c); is a consensus expression for minority. assign y = (a & b & c) | (~a & b & c) | (a & ~b & c) | (a & b & ~c); is a sum of minterms but more complex. assign y = (a ^ b) & (b ^ c) & (a ^ c); uses XOR which does not represent majority.

3. Final Answer:

   assign y = (a & b) | (b & c) | (a & c); -> Option A

4. Quick Check:

   Majority = OR of pairs ANDed = assign y = (a & b) | (b & c) | (a & c); [OK]

Hint: Majority = OR of all pairs ANDed [OK]

Common Mistakes:

• Using XOR instead of AND/OR
• Writing overly complex sum of minterms
• Confusing majority with minority logic