How Verilog maps to physical gates - Practice Exercises

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple combinational logic module

What is the output of this Verilog module when inputs A=1 and B=0?

Verilog

module simple_and(input A, input B, output Y);
  assign Y = A & B;
endmodule

A Y = 0

B Y = X (undefined)

C Compilation error

D Y = 1

💡 Hint

AND gate outputs 1 only if both inputs are 1.

The module implements an AND gate. Since A=1 and B=0, output Y = 1 & 0 = 0.

🧠 Conceptual

intermediate

Mapping Verilog always block to gates

Which physical gate does this Verilog always block represent?

Verilog

always @(*) begin
  Y = ~(A | B);
end

A AND gate

B NAND gate

C NOR gate

D OR gate

💡 Hint

The output is the negation of the OR of inputs.

The expression Y = ~(A | B) is the definition of a NOR gate.

🔧 Debug

advanced

Identify the error in gate-level mapping

What error will occur when synthesizing this Verilog code?

Verilog

module error_module(input A, input B, output Y);
  assign Y = A & B | ;
endmodule

A SyntaxError due to incomplete expression

B Y will always be 0

C Y will always be 1

D No error, compiles fine

💡 Hint

Check the assign statement for completeness.

The assign statement ends with an operator '|' without a right operand, causing a syntax error.

❓ Predict Output

advanced

Output of a D flip-flop module

What is the output Q after the rising edge of clk if D=1 and initial Q=0?

Verilog

module dff(input clk, input D, output reg Q);
  always @(posedge clk) begin
    Q <= D;
  end
endmodule

A Q = 0

B Q = 1

C Q is undefined

D Q toggles

💡 Hint

D flip-flop captures input D on rising clock edge.

On the rising edge of clk, Q takes the value of D, which is 1.

🧠 Conceptual

expert

Physical gate count from Verilog code

How many 2-input NAND gates are needed to implement this Verilog expression in CMOS?

Verilog

assign Y = ~(A & B);

A 4 NAND gates

B 2 NAND gates

C 3 NAND gates

D 1 NAND gate

💡 Hint

A NAND gate outputs the negation of AND inputs.

The expression Y = ~(A & B) is exactly a NAND gate, so only one 2-input NAND gate is needed.

Practice

1. Which Verilog construct directly represents a physical AND gate in hardware?

easy

A. reg out; out = ~a;

B. assign out = a & b;

C. wire out = a ^ b;

D. always @(posedge clk) out <= a | b;

Solution

1. Step 1: Identify the logic operation in each statement

   assign out = a & b; uses bitwise AND (&), which maps to an AND gate. always @(posedge clk) out <= a | b; uses OR (|) but inside an always block with clock, so it implies sequential logic, not a simple AND gate. wire out = a ^ b; uses XOR (^), which maps to XOR gate. reg out; out = ~a; uses NOT (~), which maps to NOT gate.

2. Step 2: Match the operation to the physical gate

   The AND operation in assign out = a & b; directly corresponds to a physical AND gate in hardware.

3. Final Answer:

   assign out = a & b; -> Option B

4. Quick Check:

   AND operation = assign out = a & b; [OK]

Hint: Bitwise & in assign maps to AND gate [OK]

Common Mistakes:

• Confusing sequential always block with combinational gate
• Mixing bitwise and logical operators
• Assuming reg implies a gate directly

2. Which of the following is the correct Verilog syntax to instantiate a 2-input NAND gate named nand1?

easy

A. nand (out, in1, in2) nand1;

B. and nand1 (out, in1, in2);

C. nand1 nand (out, in1, in2);

D. nand nand1 (out, in1, in2);

Solution

1. Step 1: Recall the gate instantiation syntax in Verilog

   The syntax is: gate_type instance_name (output, input1, input2, ...);

2. Step 2: Match the syntax to the options

   nand nand1 (out, in1, in2); matches the correct syntax with gate type nand, instance name nand1, and ports in correct order. Other options have incorrect order or wrong keywords.

3. Final Answer:

   nand nand1 (out, in1, in2); -> Option D

4. Quick Check:

   Gate instantiation = nand nand1 (out, in1, in2); [OK]

Hint: Gate type first, then instance name, then ports [OK]

Common Mistakes:

• Swapping instance name and gate type
• Incorrect port order
• Using invalid syntax like missing semicolon

3. Given the Verilog code:

assign y = ~(a & b) | c;

What is the equivalent logic gate expression for output y?

medium

A. y = (a NAND b) OR c

B. y = (a AND b) NOR c

C. y = (a OR b) NAND c

D. y = (a NOR b) AND c

Solution

1. Step 1: Analyze the expression ~(a & b) | c

   The expression first computes a & b, then negates it (~), which is NAND operation. Then it ORs the result with c.

2. Step 2: Translate to gate-level expression

   This matches (a NAND b) OR c exactly.

3. Final Answer:

   y = (a NAND b) OR c -> Option A

4. Quick Check:

   ~(a & b) = NAND, then OR with c = y = (a NAND b) OR c [OK]

Hint: ~(a & b) means NAND of a and b [OK]

Common Mistakes:

• Confusing NOR with NAND
• Misreading operator precedence
• Ignoring the negation on AND

4. Identify the error in this Verilog code snippet that tries to implement a 2-input OR gate:

module or_gate(output y, input a, b);
  wire y;
  assign y = a | b;
endmodule

medium

A. Using assign inside module is not allowed

B. Missing semicolon after assign statement

C. Declaring output y as wire inside the module causes conflict

D. Input ports a and b must be declared as reg

Solution

1. Step 1: Check port and internal signal declarations

   The output y is declared as a port and then redeclared as a wire inside the module, which causes a conflict.

2. Step 2: Understand Verilog rules for output ports

   Output ports default to wire type; redeclaring them as wire inside the module is redundant and causes error.

3. Final Answer:

   Declaring output y as wire inside the module causes conflict -> Option C

4. Quick Check:

   Output redeclaration error = Declaring output y as wire inside the module causes conflict [OK]

Hint: Don't redeclare output ports as wire inside module [OK]

Common Mistakes:

• Thinking assign needs semicolon error
• Believing inputs must be reg
• Assuming assign is disallowed inside modules

5. You want to implement a 3-input majority gate in Verilog that outputs 1 if at least two inputs are 1. Which of the following Verilog expressions correctly maps to the minimal physical gate implementation?

hard

A. assign y = (a & b) | (b & c) | (a & c);

B. assign y = (a | b) & (b | c) & (a | c);

C. assign y = (a & b & c) | (~a & b & c) | (a & ~b & c) | (a & b & ~c);

D. assign y = (a ^ b) & (b ^ c) & (a ^ c);

Solution

1. Step 1: Understand majority gate logic

   A 3-input majority gate outputs 1 if at least two inputs are 1. This is equivalent to the OR of all pairs ANDed together.

2. Step 2: Analyze each expression

   assign y = (a & b) | (b & c) | (a & c); uses OR of all pairs ANDed: (a & b) | (b & c) | (a & c), which is minimal and correct. assign y = (a | b) & (b | c) & (a | c); is a consensus expression for minority. assign y = (a & b & c) | (~a & b & c) | (a & ~b & c) | (a & b & ~c); is a sum of minterms but more complex. assign y = (a ^ b) & (b ^ c) & (a ^ c); uses XOR which does not represent majority.

3. Final Answer:

   assign y = (a & b) | (b & c) | (a & c); -> Option A

4. Quick Check:

   Majority = OR of pairs ANDed = assign y = (a & b) | (b & c) | (a & c); [OK]

Hint: Majority = OR of all pairs ANDed [OK]

Common Mistakes:

• Using XOR instead of AND/OR
• Writing overly complex sum of minterms
• Confusing majority with minority logic