Hardware description vs software programming in Verilog - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit register in Verilog.

Verilog

reg [[1]:0] my_reg;

Drag options to blanks, or click blank then click option'

A1

B4

C7

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 instead of 3 as the highest index.

Confusing bit width with index.

In Verilog, a 4-bit register is declared as reg [3:0] because counting starts from 0.

2fill in blank

medium

Complete the code to assign a value to a wire in Verilog.

Verilog

assign my_wire = [1];

Drag options to blanks, or click blank then click option'

A5'b10101

Bwire_value

Creg_value

Dinteger_value

Attempts:

3 left

💡 Hint

Common Mistakes

Trying to assign a register directly to a wire without using assign.

Using an undefined variable.

The assign statement connects a wire to a value or expression. Here, 5'b10101 is a 5-bit binary constant.

3fill in blank

hard

Fix the error in the always block sensitivity list.

Verilog

always @([1]) begin
  q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk or negedge rst

Bclk or rst

Cposedge clk and negedge rst

Dposedge clk, negedge rst

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'and' instead of 'or' in sensitivity list.

Omitting edge keywords.

The sensitivity list should use or to separate signals, and include edge keywords like posedge or negedge.

4fill in blank

hard

Fill both blanks to create a combinational always block that triggers on any input change.

Verilog

always @([1]) begin
  y = a [2] b;
end

Drag options to blanks, or click blank then click option'

A*

B+

C-

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'posedge clk' for combinational logic.

Using '-' instead of '+' for addition.

The always @(*) block triggers on any input change, and y = a + b; adds the inputs combinationally.

5fill in blank

hard

Fill all three blanks to create a simple synchronous counter.

Verilog

always @([1]) begin
  if ([2]) begin
    count <= 0;
  end else begin
    count <= count [3] 1;
  end
end

Drag options to blanks, or click blank then click option'

Aposedge clk

Brst

C+

Dnegedge rst

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'negedge rst' in sensitivity list instead of clock.

Using '-' instead of '+' for increment.

The always block triggers on the positive edge of the clock. If reset (rst) is active, the counter resets to 0; otherwise, it increments by 1.

Practice

1. Which statement best describes the main difference between hardware description languages like Verilog and software programming languages?

easy

A. Hardware description languages define circuits and connections, while software programming languages define instructions and logic flow.

B. Hardware description languages run on computers, software programming languages run on microcontrollers.

C. Hardware description languages are only used for graphics, software programming languages are for calculations.

D. Hardware description languages are slower than software programming languages.

Solution

1. Step 1: Understand the purpose of hardware description languages

   Hardware description languages like Verilog describe how electronic circuits are built and connected.

2. Step 2: Understand the purpose of software programming languages

   Software programming languages describe instructions and logic that a computer executes step-by-step.

3. Final Answer:

   Hardware description languages define circuits and connections, while software programming languages define instructions and logic flow. -> Option A

4. Quick Check:

   Hardware description = circuits, Software programming = instructions [OK]

Hint: Hardware = circuits, Software = instructions [OK]

Common Mistakes:

• Confusing hardware description as software code
• Thinking hardware languages run on microcontrollers
• Assuming hardware languages are slower

2. Which of the following is the correct way to declare a 4-bit wire in Verilog?

easy

A. wire my_wire = 4;

B. wire [3:0] my_wire;

C. wire my_wire[4];

D. wire my_wire(4);

Solution

1. Step 1: Recall Verilog syntax for wire declaration

   In Verilog, a wire vector is declared with the range in square brackets before the name, e.g., wire [3:0] name;

2. Step 2: Check each option

   wire [3:0] my_wire; uses correct syntax. Options A, B, and D use invalid syntax for wire declaration.

3. Final Answer:

   wire [3:0] my_wire; -> Option B

4. Quick Check:

   Wire vector syntax = wire [3:0] name [OK]

Hint: Use square brackets before name for bit width [OK]

Common Mistakes:

• Placing size after the name
• Using parentheses instead of brackets
• Assigning a number directly to wire

3. What will be the output of the following Verilog code snippet?

module test;
  reg [1:0] a = 2'b10;
  reg [1:0] b = 2'b01;
  wire [1:0] c;
  assign c = a & b;
  initial begin
    $display("%b", c);
  end
endmodule

medium

A. 10

B. 01

C. 00

D. 11

Solution

1. Step 1: Understand bitwise AND operation

   Bitwise AND compares each bit of 'a' and 'b': 1 & 0 = 0, 0 & 1 = 0.

2. Step 2: Calculate c = a & b

   a = 10, b = 01, so c = 00 in binary.

3. Final Answer:

   00 -> Option C

4. Quick Check:

   2'b10 & 2'b01 = 2'b00 [OK]

Hint: AND bits one by one for result [OK]

Common Mistakes:

• Confusing bitwise AND with OR
• Reading bits left to right incorrectly
• Expecting decimal output instead of binary

4. Identify the error in this Verilog code snippet:

module example;
  reg [3:0] data;
  initial begin
    data = 4'b1010;
    if (data == 4'b1010)
      $display("Match");
    else
      $display("No match");
  end
endmodule

medium

A. The 'if' condition syntax is incorrect.

B. The bit width of 'data' is too small.

C. The 'data' register is not initialized properly.

D. The code is correct and will print 'Match'.

Solution

1. Step 1: Check register initialization

   Register 'data' is assigned 4'b1010 correctly inside initial block.

2. Step 2: Check if condition and display statements

   The if condition compares 'data' to 4'b1010 correctly and will print 'Match'.

3. Final Answer:

   The code is correct and will print 'Match'. -> Option D

4. Quick Check:

   Correct syntax and logic = prints 'Match' [OK]

Hint: Check if conditions and assignments carefully [OK]

Common Mistakes:

• Thinking 'if' syntax needs parentheses around condition
• Assuming registers need special initialization
• Confusing bit width sizes

5. You want to model a simple 2-to-1 multiplexer in Verilog that selects between two 4-bit inputs a and b based on a select signal sel. Which code snippet correctly describes this hardware behavior?

hard

A. assign out = sel ? a : b;

B. if (sel == 1) out = a; else out = b;

C. out = a + b * sel;

D. always @(sel) out = sel & a | sel & b;

Solution

1. Step 1: Understand multiplexer behavior

   A 2-to-1 mux outputs 'a' if sel=1, else 'b'.

2. Step 2: Check each code snippet

   assign out = sel ? a : b; uses a conditional operator to select output correctly. if (sel == 1) out = a; else out = b; is procedural and incomplete without always block. out = a + b * sel; uses arithmetic, not selection. always @(sel) out = sel & a | ~sel & b; uses bitwise operators incorrectly for mux.

3. Final Answer:

   assign out = sel ? a : b; -> Option A

4. Quick Check:

   Conditional operator models mux correctly [OK]

Hint: Use conditional operator for simple mux [OK]

Common Mistakes:

• Using arithmetic instead of selection
• Missing always block for procedural code
• Confusing bitwise operators with mux logic