Hardware description vs software programming in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of Verilog procedural block

What is the output of the following Verilog code when the clock triggers?

Verilog

module test;
  reg clk = 0;
  reg [1:0] state = 2'b00;
  always @(posedge clk) begin
    state <= state + 1;
  end
  initial begin
    #1 clk = 1;
    #1 clk = 0;
    #1 clk = 1;
    #1 clk = 0;
    $display("State: %b", state);
  end
endmodule

A State: 10

B State: 11

C State: 01

D State: 00

💡 Hint

Remember that state updates on the positive edge of clk and uses non-blocking assignment.

The state increments twice on two positive edges of clk, starting from 00, so it becomes 01 then 10.

🧠 Conceptual

intermediate

Difference between hardware description and software programming

Which statement best describes a key difference between hardware description languages (HDL) like Verilog and software programming languages?

A HDLs run on CPUs; software languages run on FPGAs.

B HDLs describe hardware structure and parallel behavior; software languages describe sequential instructions executed by a CPU.

C HDLs are interpreted line-by-line; software languages are compiled into hardware circuits.

D HDLs cannot describe timing; software languages control hardware timing precisely.

💡 Hint

Think about how HDLs model circuits versus how software runs on processors.

HDLs describe hardware components and their parallel operation, while software languages provide sequential instructions for CPUs.

🔧 Debug

advanced

Identify the error in this Verilog code snippet

What error will this Verilog code produce when synthesized or simulated?

Verilog

module counter(input clk, output reg [1:0] count);
  always @(clk) begin
    count = count + 1;
  end
endmodule

A No error; code works as expected.

B Count will not increment correctly because 'always @(clk)' triggers on any change, not just posedge.

C Runtime error: 'count' is not declared as wire.

D Synthesis error: missing 'posedge' in sensitivity list for sequential logic.

💡 Hint

Sequential logic requires edge-triggered sensitivity.

The sensitivity list should use 'posedge clk' for proper sequential behavior; otherwise synthesis tools will error.

📝 Syntax

advanced

Which Verilog code snippet correctly models a 2-bit register with asynchronous reset?

Select the code that correctly implements a 2-bit register with asynchronous active-low reset.

A

always @(posedge clk) begin
  if (!rst_n) reg_out <= 2'b00;
  else reg_out <= data_in;
end

B

always @(posedge clk or posedge rst_n) begin
  if (rst_n) reg_out <= 2'b00;
  else reg_out <= data_in;
end

C

always @(posedge clk or negedge rst_n) begin
  if (!rst_n) reg_out <= 2'b00;
  else reg_out <= data_in;
end

D

always @(negedge clk or negedge rst_n) begin
  if (!rst_n) reg_out <= 2'b00;
  else reg_out <= data_in;
end

💡 Hint

Asynchronous reset triggers on reset signal edge, not clock edge.

Option C correctly uses posedge clk and negedge rst_n in sensitivity list and resets asynchronously when rst_n is low.

🚀 Application

expert

Predict the final value of a register after mixed blocking and non-blocking assignments

Given the following Verilog code, what is the final value of 'reg_a' after the always block executes on a positive clock edge?

Verilog

module test;
  reg clk = 0;
  reg [3:0] reg_a = 4'b0000;
  always @(posedge clk) begin
    reg_a = reg_a + 1; // blocking assignment
    reg_a <= reg_a + 1; // non-blocking assignment
  end
  initial begin
    #1 clk = 1;
    #1 clk = 0;
    #1 $display("reg_a = %b", reg_a);
  end
endmodule

A reg_a = 0010

B reg_a = 0011

C reg_a = 0001

D reg_a = 0000

💡 Hint

Remember how blocking and non-blocking assignments interact in the same always block.

The blocking assignment updates reg_a immediately to 0001, then the non-blocking schedules reg_a to be updated to 0001 + 1 = 0010 after the block.

Practice

1. Which statement best describes the main difference between hardware description languages like Verilog and software programming languages?

easy

A. Hardware description languages define circuits and connections, while software programming languages define instructions and logic flow.

B. Hardware description languages run on computers, software programming languages run on microcontrollers.

C. Hardware description languages are only used for graphics, software programming languages are for calculations.

D. Hardware description languages are slower than software programming languages.

Solution

1. Step 1: Understand the purpose of hardware description languages

   Hardware description languages like Verilog describe how electronic circuits are built and connected.

2. Step 2: Understand the purpose of software programming languages

   Software programming languages describe instructions and logic that a computer executes step-by-step.

3. Final Answer:

   Hardware description languages define circuits and connections, while software programming languages define instructions and logic flow. -> Option A

4. Quick Check:

   Hardware description = circuits, Software programming = instructions [OK]

Hint: Hardware = circuits, Software = instructions [OK]

Common Mistakes:

• Confusing hardware description as software code
• Thinking hardware languages run on microcontrollers
• Assuming hardware languages are slower

2. Which of the following is the correct way to declare a 4-bit wire in Verilog?

easy

A. wire my_wire = 4;

B. wire [3:0] my_wire;

C. wire my_wire[4];

D. wire my_wire(4);

Solution

1. Step 1: Recall Verilog syntax for wire declaration

   In Verilog, a wire vector is declared with the range in square brackets before the name, e.g., wire [3:0] name;

2. Step 2: Check each option

   wire [3:0] my_wire; uses correct syntax. Options A, B, and D use invalid syntax for wire declaration.

3. Final Answer:

   wire [3:0] my_wire; -> Option B

4. Quick Check:

   Wire vector syntax = wire [3:0] name [OK]

Hint: Use square brackets before name for bit width [OK]

Common Mistakes:

• Placing size after the name
• Using parentheses instead of brackets
• Assigning a number directly to wire

3. What will be the output of the following Verilog code snippet?

module test;
  reg [1:0] a = 2'b10;
  reg [1:0] b = 2'b01;
  wire [1:0] c;
  assign c = a & b;
  initial begin
    $display("%b", c);
  end
endmodule

medium

A. 10

B. 01

C. 00

D. 11

Solution

1. Step 1: Understand bitwise AND operation

   Bitwise AND compares each bit of 'a' and 'b': 1 & 0 = 0, 0 & 1 = 0.

2. Step 2: Calculate c = a & b

   a = 10, b = 01, so c = 00 in binary.

3. Final Answer:

   00 -> Option C

4. Quick Check:

   2'b10 & 2'b01 = 2'b00 [OK]

Hint: AND bits one by one for result [OK]

Common Mistakes:

• Confusing bitwise AND with OR
• Reading bits left to right incorrectly
• Expecting decimal output instead of binary

4. Identify the error in this Verilog code snippet:

module example;
  reg [3:0] data;
  initial begin
    data = 4'b1010;
    if (data == 4'b1010)
      $display("Match");
    else
      $display("No match");
  end
endmodule

medium

A. The 'if' condition syntax is incorrect.

B. The bit width of 'data' is too small.

C. The 'data' register is not initialized properly.

D. The code is correct and will print 'Match'.

Solution

1. Step 1: Check register initialization

   Register 'data' is assigned 4'b1010 correctly inside initial block.

2. Step 2: Check if condition and display statements

   The if condition compares 'data' to 4'b1010 correctly and will print 'Match'.

3. Final Answer:

   The code is correct and will print 'Match'. -> Option D

4. Quick Check:

   Correct syntax and logic = prints 'Match' [OK]

Hint: Check if conditions and assignments carefully [OK]

Common Mistakes:

• Thinking 'if' syntax needs parentheses around condition
• Assuming registers need special initialization
• Confusing bit width sizes

5. You want to model a simple 2-to-1 multiplexer in Verilog that selects between two 4-bit inputs a and b based on a select signal sel. Which code snippet correctly describes this hardware behavior?

hard

A. assign out = sel ? a : b;

B. if (sel == 1) out = a; else out = b;

C. out = a + b * sel;

D. always @(sel) out = sel & a | sel & b;

Solution

1. Step 1: Understand multiplexer behavior

   A 2-to-1 mux outputs 'a' if sel=1, else 'b'.

2. Step 2: Check each code snippet

   assign out = sel ? a : b; uses a conditional operator to select output correctly. if (sel == 1) out = a; else out = b; is procedural and incomplete without always block. out = a + b * sel; uses arithmetic, not selection. always @(sel) out = sel & a | ~sel & b; uses bitwise operators incorrectly for mux.

3. Final Answer:

   assign out = sel ? a : b; -> Option A

4. Quick Check:

   Conditional operator models mux correctly [OK]

Hint: Use conditional operator for simple mux [OK]

Common Mistakes:

• Using arithmetic instead of selection
• Missing always block for procedural code
• Confusing bitwise operators with mux logic