First Verilog module (AND gate) - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a Verilog module?

A Verilog module is like a small building block or a box that contains a piece of hardware design. It has inputs and outputs and describes how signals connect inside.

beginner

What does an AND gate do?

An AND gate outputs 1 only if all its inputs are 1. Otherwise, it outputs 0. Think of it like a rule: "All conditions must be true to get true."

beginner

How do you declare inputs and outputs in a Verilog module?

Inside the module, you list inputs and outputs using the keywords input and output. For example, input a, b; and output c;.

beginner

What is the purpose of the assign statement in Verilog?

The assign statement connects outputs to expressions of inputs. It tells the hardware how to calculate the output continuously.

beginner

Write a simple Verilog module for a 2-input AND gate.

module and_gate(input a, input b, output c); assign c = a & b; endmodule

What keyword starts a Verilog module?

A start

B begin

C function

D module

A Verilog module always starts with the keyword module.

What output does an AND gate produce if one input is 0 and the other is 1?

A 0

B Undefined

C Depends on the clock

D 1

An AND gate outputs 1 only if all inputs are 1. Here, one input is 0, so output is 0.

Which statement continuously connects output to inputs in Verilog?

A reg

B wire

C assign

D always

The assign statement is used for continuous assignment in Verilog.

How do you declare an output named 'c' in a Verilog module?

A input c;

B output c;

C wire c;

D reg c;

Outputs are declared with the keyword output.

What symbol is used for the AND operation in Verilog?

A &

B |

C ^

D ~

The AND operation uses the ampersand & symbol.

Explain how to create a simple 2-input AND gate module in Verilog.

Think about the parts of a module: start, inputs, outputs, logic, end.

Describe what an AND gate does and how it is represented in Verilog code.

Focus on the logic behavior and the Verilog syntax.

Practice

1. What does a Verilog module for an AND gate do?

easy

A. It displays images on the screen.

B. It runs a program to calculate numbers.

C. It stores data like a memory chip.

D. It describes how the AND gate connects inputs to produce an output.

Solution

1. Step 1: Understand the purpose of a Verilog module

   A Verilog module models hardware behavior, like logic gates, using code.

2. Step 2: Identify the role of an AND gate module

   The AND gate module connects inputs with an AND operation to produce an output signal.

3. Final Answer:

   It describes how the AND gate connects inputs to produce an output. -> Option D

4. Quick Check:

   Verilog module = hardware description [OK]

Hint: Think hardware, not software programs [OK]

Common Mistakes:

• Confusing Verilog module with software code
• Thinking it stores data like memory
• Assuming it displays graphics

2. Which of the following is the correct way to declare inputs and outputs in a Verilog AND gate module?

easy

A. module and_gate(input c, output a, input b);

B. module and_gate(output a, output b, input c);

C. module and_gate(input a, input b, output c);

D. module and_gate(output c, input a input b);

Solution

1. Step 1: Recall Verilog input/output declaration order

   Inputs are declared first, then outputs, inside the module header.

2. Step 2: Check each option's order

   module and_gate(input a, input b, output c); correctly declares inputs 'a' and 'b' first, then output 'c'.

3. Final Answer:

   module and_gate(input a, input b, output c); -> Option C

4. Quick Check:

   Inputs before outputs in module header [OK]

Hint: Inputs come before outputs in module declaration [OK]

Common Mistakes:

• Swapping input and output keywords
• Declaring outputs before inputs
• Mixing input/output order randomly

3. What is the output c when inputs a=1 and b=0 in this Verilog AND gate module?

module and_gate(input a, input b, output c);
  assign c = a & b;
endmodule

medium

A. 0

B. 1

C. Z (high impedance)

D. X (unknown)

Solution

1. Step 1: Understand AND operation on inputs

   AND gate outputs 1 only if both inputs are 1; otherwise 0.

2. Step 2: Apply inputs a=1 and b=0

   1 & 0 = 0, so output c is 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   1 AND 0 = 0 [OK]

Hint: AND is 1 only if both inputs are 1 [OK]

Common Mistakes:

• Thinking output is 1 if any input is 1
• Confusing AND with OR gate
• Assuming output is unknown or high impedance

4. Identify the error in this Verilog AND gate module:

module and_gate(input a, input b, output c)
  assign c = a & b;
endmodule

medium

A. Incorrect use of assign keyword

B. Missing semicolon after module declaration

C. Wrong operator used for AND

D. No error, code is correct

Solution

1. Step 1: Check module declaration syntax

   Module header must end with a semicolon (;).

2. Step 2: Locate missing semicolon

   After the module declaration line, the semicolon is missing.

3. Final Answer:

   Missing semicolon after module declaration -> Option B

4. Quick Check:

   Module header needs semicolon [OK]

Hint: Always end module header with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after module line
• Misusing assign keyword
• Using wrong operator for AND

5. You want to create a Verilog module that ANDs three inputs a, b, and c to produce output y. Which code correctly implements this?

hard

A. module and3(input a, input b, input c, output y);
assign y = a & b & c;
endmodule

B. module and3(input a, input b, output y);
assign y = a & b & c;
endmodule

C. module and3(input a, input b, input c, output y);
assign y = a | b | c;
endmodule

D. module and3(input a, input b, input c, output y);
assign y = a & b;
endmodule

Solution

1. Step 1: Check input and output declarations

   All three inputs a, b, c and output y must be declared in the module header.

2. Step 2: Verify the assign statement logic

   Output y should be the AND of all three inputs: a & b & c.

3. Step 3: Eliminate incorrect options

   module and3(input a, input b, output y); assign y = a & b & c; endmodule misses input c declaration; one uses OR instead of AND; another misses input c in logic.

4. Final Answer:

   module and3(input a, input b, input c, output y); assign y = a & b & c; endmodule -> Option A

5. Quick Check:

   All inputs declared and ANDed correctly [OK]

Hint: Declare all inputs and AND them in assign [OK]

Common Mistakes:

• Forgetting to declare all inputs
• Using OR instead of AND
• Not including all inputs in assign