First Verilog module (AND gate) - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ trace

intermediate

What is the output of this AND gate module for inputs A=1, B=0?

Consider this Verilog module for a simple AND gate:

module and_gate(input A, input B, output Y);
  assign Y = A & B;
endmodule

What is the value of output Y when A=1 and B=0?

Verilog

module and_gate(input A, input B, output Y);
  assign Y = A & B;
endmodule

A Y = 0

B Y = 2

C Y = X (unknown)

D Y = 1

💡 Hint

AND gate outputs 1 only if both inputs are 1.

An AND gate outputs 1 only when both inputs are 1. Since B=0, output Y is 0.

🧠 Conceptual

intermediate

Which part of the Verilog module defines the output?

In the following Verilog module, which keyword defines the output signal?

module and_gate(input A, input B, output Y);
  assign Y = A & B;
endmodule

Verilog

module and_gate(input A, input B, output Y);
  assign Y = A & B;
endmodule

A input

B output

C assign

D module

💡 Hint

Look for the keyword that declares signals that come out of the module.

The keyword output declares signals that the module sends out, like Y here.

❓ identification

advanced

Which option causes a syntax error in this AND gate module?

Identify the option that will cause a syntax error when defining an AND gate module.

A

module and_gate(input A, input B, output Y);
  assign Y = A & B;
endmodule

B

module and_gate(input A, input B, output Y);
  assign Y = A && B;
endmodule

C

module and_gate(input A, input B, output Y);
  assign Y = A & B;
end module

D

module and_gate(input A, input B, output Y)
  assign Y = A & B;
endmodule

💡 Hint

Check for missing punctuation or incorrect keywords.

Option D is missing a semicolon after the module declaration line, causing a syntax error.

❓ Comparison

advanced

Which option correctly uses the bitwise AND operator in Verilog?

Choose the option that correctly uses the bitwise AND operator to assign output Y in a Verilog module.

A assign Y = A | B;

B assign Y = A && B;

C assign Y = A & B;

D assign Y = A + B;

💡 Hint

Bitwise AND uses a single ampersand.

In Verilog, & is bitwise AND, while && is logical AND (not used for bitwise operations).

🚀 Application

expert

What is the output vector Y for inputs A=4'b1101 and B=4'b1011 in this AND gate module?

Given this 4-bit AND gate module:

module and_gate_4bit(input [3:0] A, input [3:0] B, output [3:0] Y);
  assign Y = A & B;
endmodule

What is the value of Y when A = 4'b1101 and B = 4'b1011?

Verilog

module and_gate_4bit(input [3:0] A, input [3:0] B, output [3:0] Y);
  assign Y = A & B;
endmodule

A 4'b1001

B 4'b1111

C 4'b1100

D 4'b1010

💡 Hint

Perform bitwise AND on each bit position.

Bitwise AND of 1101 and 1011 is 1001:
1&1=1, 1&0=0, 0&1=0, 1&1=1

Practice

1. What does a Verilog module for an AND gate do?

easy

A. It displays images on the screen.

B. It runs a program to calculate numbers.

C. It stores data like a memory chip.

D. It describes how the AND gate connects inputs to produce an output.

Solution

1. Step 1: Understand the purpose of a Verilog module

   A Verilog module models hardware behavior, like logic gates, using code.

2. Step 2: Identify the role of an AND gate module

   The AND gate module connects inputs with an AND operation to produce an output signal.

3. Final Answer:

   It describes how the AND gate connects inputs to produce an output. -> Option D

4. Quick Check:

   Verilog module = hardware description [OK]

Hint: Think hardware, not software programs [OK]

Common Mistakes:

• Confusing Verilog module with software code
• Thinking it stores data like memory
• Assuming it displays graphics

2. Which of the following is the correct way to declare inputs and outputs in a Verilog AND gate module?

easy

A. module and_gate(input c, output a, input b);

B. module and_gate(output a, output b, input c);

C. module and_gate(input a, input b, output c);

D. module and_gate(output c, input a input b);

Solution

1. Step 1: Recall Verilog input/output declaration order

   Inputs are declared first, then outputs, inside the module header.

2. Step 2: Check each option's order

   module and_gate(input a, input b, output c); correctly declares inputs 'a' and 'b' first, then output 'c'.

3. Final Answer:

   module and_gate(input a, input b, output c); -> Option C

4. Quick Check:

   Inputs before outputs in module header [OK]

Hint: Inputs come before outputs in module declaration [OK]

Common Mistakes:

• Swapping input and output keywords
• Declaring outputs before inputs
• Mixing input/output order randomly

3. What is the output c when inputs a=1 and b=0 in this Verilog AND gate module?

module and_gate(input a, input b, output c);
  assign c = a & b;
endmodule

medium

A. 0

B. 1

C. Z (high impedance)

D. X (unknown)

Solution

1. Step 1: Understand AND operation on inputs

   AND gate outputs 1 only if both inputs are 1; otherwise 0.

2. Step 2: Apply inputs a=1 and b=0

   1 & 0 = 0, so output c is 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   1 AND 0 = 0 [OK]

Hint: AND is 1 only if both inputs are 1 [OK]

Common Mistakes:

• Thinking output is 1 if any input is 1
• Confusing AND with OR gate
• Assuming output is unknown or high impedance

4. Identify the error in this Verilog AND gate module:

module and_gate(input a, input b, output c)
  assign c = a & b;
endmodule

medium

A. Incorrect use of assign keyword

B. Missing semicolon after module declaration

C. Wrong operator used for AND

D. No error, code is correct

Solution

1. Step 1: Check module declaration syntax

   Module header must end with a semicolon (;).

2. Step 2: Locate missing semicolon

   After the module declaration line, the semicolon is missing.

3. Final Answer:

   Missing semicolon after module declaration -> Option B

4. Quick Check:

   Module header needs semicolon [OK]

Hint: Always end module header with semicolon [OK]

Common Mistakes:

• Forgetting semicolon after module line
• Misusing assign keyword
• Using wrong operator for AND

5. You want to create a Verilog module that ANDs three inputs a, b, and c to produce output y. Which code correctly implements this?

hard

A. module and3(input a, input b, input c, output y);
assign y = a & b & c;
endmodule

B. module and3(input a, input b, output y);
assign y = a & b & c;
endmodule

C. module and3(input a, input b, input c, output y);
assign y = a | b | c;
endmodule

D. module and3(input a, input b, input c, output y);
assign y = a & b;
endmodule

Solution

1. Step 1: Check input and output declarations

   All three inputs a, b, c and output y must be declared in the module header.

2. Step 2: Verify the assign statement logic

   Output y should be the AND of all three inputs: a & b & c.

3. Step 3: Eliminate incorrect options

   module and3(input a, input b, output y); assign y = a & b & c; endmodule misses input c declaration; one uses OR instead of AND; another misses input c in logic.

4. Final Answer:

   module and3(input a, input b, input c, output y); assign y = a & b & c; endmodule -> Option A

5. Quick Check:

   All inputs declared and ANDed correctly [OK]

Hint: Declare all inputs and AND them in assign [OK]

Common Mistakes:

• Forgetting to declare all inputs
• Using OR instead of AND
• Not including all inputs in assign