Bit vectors and bus declaration in Verilog - Step-by-Step Execution

Concept Flow - Bit vectors and bus declaration

Start

↓

Declare bit vector

↓

Assign values to bits

↓

Use vector in logic

↓

Access individual bits

↓

End

This flow shows how a bit vector (bus) is declared, assigned, and used step-by-step in Verilog.

Execution Sample

Verilog

reg [3:0] bus;
initial begin
  bus = 4'b1010;
  $display("bus = %b", bus);
  $display("bit 2 = %b", bus[2]);
end

Declares a 4-bit bus, assigns a binary value, then prints the whole bus and one bit.

Execution Table

Step	Action	bus value	Accessed bit	Output
1	Declare bus as 4 bits	xxxx	-	-
2	Assign bus = 4'b1010	1010	-	-
3	Display bus	1010	-	bus = 1010
4	Display bus[2]	1010	1	bit 2 = 1
5	End of initial block	1010	-	-

💡 Initial block finishes after displaying bus and bit 2 values.

Variable Tracker

Variable	Start	After 2	Final
bus	xxxx	1010	1010
bus[2]	-	1	1

Key Moments - 3 Insights

Why does bus start as 'xxxx' before assignment?

Before assignment, the bus bits are undefined (shown as 'x'), as seen in step 1 of the execution_table.

How do we access a single bit from the bus?

Use bus[index], for example bus[2] accesses the third bit, shown in step 4 where bus[2] is 1.

What does the notation [3:0] mean in bus declaration?

It declares a 4-bit bus with bits numbered 3 down to 0, meaning bus has 4 bits total, as shown in step 1.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of bus at step 2?

A 0101

B 1010

C xxxx

D 1111

💡 Hint

Check the 'bus value' column at step 2 in the execution_table.

At which step is the bit 2 of bus accessed?

A Step 4

B Step 1

C Step 3

D Step 5

💡 Hint

Look for 'Accessed bit' column in execution_table where bus[2] is shown.

If bus was declared as reg [7:0] bus; how many bits would it have?

A 4 bits

B 7 bits

C 8 bits

D 1 bit

💡 Hint

The range [7:0] means bits from 7 down to 0, total 8 bits.

Concept Snapshot

Bit vectors (buses) are declared with [msb:lsb], e.g., reg [3:0] bus;
Each bit can be accessed by bus[index], index 0 is least significant bit.
Before assignment, bits are undefined (x).
Assign values using binary notation like 4'b1010.
Use $display to print bus or individual bits.

Full Transcript

This example shows how to declare a 4-bit bus in Verilog using reg [3:0] bus. Initially, the bus bits are undefined, shown as 'x'. Then we assign the binary value 1010 to the bus. We print the entire bus value and also print the value of bit 2 (third bit from right). The bit 2 value is 1. This demonstrates how to declare, assign, and access bits in a bus.

Practice

1. What does the declaration wire [7:0] data_bus; represent in Verilog?

easy

A. A single wire named data_bus with value 7 or 0

B. A wire array with 7 elements each 8 bits wide

C. A wire that is 8 bits wide, from bit 7 down to bit 0

D. A wire that can only hold values 7 or 0

Solution

1. Step 1: Understand bus declaration syntax

   The syntax [7:0] means a vector from bit 7 down to bit 0, so 8 bits total.

2. Step 2: Interpret the declaration meaning

   Declaring wire [7:0] data_bus; creates a wire signal that is 8 bits wide, indexed 7 to 0.

3. Final Answer:

   A wire that is 8 bits wide, from bit 7 down to bit 0 -> Option C

4. Quick Check:

   Bit vector = 8 bits wide [OK]

Hint: Look for [msb:lsb] to find bus width quickly [OK]

Common Mistakes:

• Thinking it declares multiple wires instead of one bus
• Confusing bit range direction (7:0 vs 0:7)
• Assuming it declares a single bit wire

2. Which of the following is the correct way to declare a 16-bit register named reg16 in Verilog?

easy

A. reg [15:0] reg16;

B. reg [0:15] reg16;

C. reg16 reg [15:0];

D. reg reg16[15:0];

Solution

1. Step 1: Recall correct syntax for bus declaration

   In Verilog, the bus width is declared inside square brackets before the variable name, like reg [width] name;.

2. Step 2: Check each option

   The correct syntax is reg [15:0] reg16;. reg reg16[15:0]; uses array syntax incorrectly. reg16 reg [15:0]; has incorrect order of keywords. reg [0:15] reg16; uses a reversed bit range, which is allowed but less common and can cause confusion.

3. Final Answer:

   reg [15:0] reg16; -> Option A

4. Quick Check:

   Correct bus syntax = reg [msb:lsb] name [OK]

Hint: Bus width always goes inside [] before the name [OK]

Common Mistakes:

• Using array syntax instead of bus syntax
• Placing the bus range after the variable name
• Reversing the bit range incorrectly

3. Given the code snippet:

wire [3:0] bus;
assign bus = 4'b1010;
wire bit0 = bus[0];
wire bit3 = bus[3];

What are the values of bit0 and bit3 respectively?

medium

A. bit0 = 0, bit3 = 1

B. bit0 = 1, bit3 = 0

C. bit0 = 1, bit3 = 1

D. bit0 = 0, bit3 = 0

Solution

1. Step 1: Understand bit indexing in bus

   The bus is assigned 4'b1010, which means bit3=1, bit2=0, bit1=1, bit0=0 (MSB to LSB).

2. Step 2: Extract bit0 and bit3 values

   bit0 is the least significant bit, which is 0. bit3 is the most significant bit, which is 1.

3. Final Answer:

   bit0 = 0, bit3 = 1 -> Option A

4. Quick Check:

   bus[3:0] = 1010, bit0=0, bit3=1 [OK]

Hint: MSB is highest index, LSB is zero index [OK]

Common Mistakes:

• Confusing bit0 with MSB instead of LSB
• Reading bits in reverse order
• Misinterpreting binary literal order

4. Identify the error in the following Verilog declaration:

wire [7:0] data;
wire [7:0] data_bus;
assign data = data_bus[8];

medium

A. Missing semicolon after assign statement

B. Index 8 is out of range for data_bus

C. Cannot assign wire to wire

D. data_bus should be declared as reg

Solution

1. Step 1: Check bus range and indexing

   data_bus is declared as 8 bits wide with indices 7 down to 0, so valid indices are 0 to 7.

2. Step 2: Identify invalid index usage

   The code tries to access data_bus[8], which is outside the declared range, causing an error.

3. Final Answer:

   Index 8 is out of range for data_bus -> Option B

4. Quick Check:

   Bus index must be within declared range [OK]

Hint: Check index is within [msb:lsb] range [OK]

Common Mistakes:

• Using index equal to bus width instead of max index
• Thinking wire-to-wire assign is invalid
• Ignoring semicolon errors

5. You want to declare a 12-bit bus named control_signal where bit 11 is the most significant bit and bit 0 is the least significant bit. Which declaration is correct and why?

Options:
A) wire [11:0] control_signal;
B) wire [0:11] control_signal;
C) wire control_signal[11:0];
D) wire control_signal[0:11];

hard

A. wire control_signal[0:11]; because this declares an array with reversed indices

B. wire [0:11] control_signal; because LSB is first index

C. wire control_signal[11:0]; because this declares an array of wires

D. wire [11:0] control_signal; because MSB must be higher index first

Solution

1. Step 1: Understand bit vector direction

   In Verilog, the most common and recommended way is to declare buses with MSB first, e.g., [11:0], so bit 11 is MSB and bit 0 is LSB.

2. Step 2: Analyze each option

   wire [11:0] control_signal; because MSB must be higher index first correctly declares a 12-bit bus with MSB=11 and LSB=0. The options with wire control_signal[11:0]; and wire control_signal[0:11]; declare arrays, not buses. wire [0:11] control_signal; because LSB is first index reverses the range, which is legal but uncommon and can cause confusion.

3. Final Answer:

   wire [11:0] control_signal; because MSB must be higher index first -> Option D

4. Quick Check:

   MSB:LSB = [11:0] for 12-bit bus [OK]

Hint: Use [msb:lsb] with MSB > LSB for clarity [OK]

Common Mistakes:

• Confusing array declaration with bus declaration
• Using reversed bit range causing indexing confusion
• Assuming [0:11] is standard for MSB to LSB