Bit vectors and bus declaration in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Understanding bit vector width and indexing

What is the value of out after this Verilog code runs?

module test;
  reg [3:0] in = 4'b1011;
  wire out;
  assign out = in[2];
endmodule

Verilog

module test;
  reg [3:0] in = 4'b1011;
  wire out;
  assign out = in[2];
endmodule

A 1

B 0

C Z (high impedance)

D 4'b1011

💡 Hint

Remember that bit indexing starts at 0 from the rightmost bit.

The vector in is 4 bits: bits 3 to 0. The bits are 1(3),0(2),1(1),1(0). So in[2] is 0.

❓ Predict Output

intermediate

Bus declaration and concatenation output

What is the 8-bit value of bus_out after this code?

module test;
  wire [3:0] a = 4'b1100;
  wire [3:0] b = 4'b0011;
  wire [7:0] bus_out;
  assign bus_out = {a, b};
endmodule

Verilog

module test;
  wire [3:0] a = 4'b1100;
  wire [3:0] b = 4'b0011;
  wire [7:0] bus_out;
  assign bus_out = {a, b};
endmodule

A 8'b00110011

B 8'b00111100

C 8'b11001100

D 8'b11000011

💡 Hint

Concatenation puts the first vector on the left (higher bits).

Concatenation {a, b} places a in bits 7:4 and b in bits 3:0, so bus_out = 1100 0011.

❓ Predict Output

advanced

Effect of reversed bit vector declaration

What is the value of out after this code?

module test;
  reg [0:3] in = 4'b1011;
  wire out;
  assign out = in[0];
endmodule

Verilog

module test;
  reg [0:3] in = 4'b1011;
  wire out;
  assign out = in[0];
endmodule

A 1

B 0

C Z (high impedance)

D Syntax error

💡 Hint

Bit vector ranges can be declared with the left index smaller than the right index.

The vector in is declared from 0 to 3, so in[0] is the leftmost bit of 4'b1011 which is 1.

❓ Predict Output

advanced

Bus slicing and output value

What is the 3-bit value of slice after this code?

module test;
  wire [7:0] bus = 8'b10110110;
  wire [2:0] slice;
  assign slice = bus[5:3];
endmodule

Verilog

module test;
  wire [7:0] bus = 8'b10110110;
  wire [2:0] slice;
  assign slice = bus[5:3];
endmodule

A 3'b110

B 3'b101

C 3'b011

D 3'b100

💡 Hint

Remember bit 7 is leftmost, bit 0 is rightmost.

bus = 10110110, bits 5 to 3 are bits 5=1,4=1,3=0, so slice = 3'b110.

🧠 Conceptual

expert

Bus declaration and default values in Verilog

Which statement about Verilog bit vector declarations is TRUE?

A Declaring <code>reg [7:0] bus;</code> initializes all bits to 0 by default.

B Declaring <code>reg [0:7] bus;</code> is invalid syntax and causes a compile error.

C Declaring <code>wire [3:0] bus;</code> without assignment leaves bits at unknown (X) state.

D Declaring <code>wire [7:0] bus = 8'bZZZZZZZZ;</code> sets all bits to logic 1.

💡 Hint

Think about default initialization of reg and wire types in Verilog.

In Verilog, reg variables keep their value until assigned, but are not automatically zeroed. wire without assignment is unknown (X). Declaring reg [0:7] is valid. Assigning 8'bZZZZZZZZ sets bits to high impedance (Z), not 1.

Practice

1. What does the declaration wire [7:0] data_bus; represent in Verilog?

easy

A. A single wire named data_bus with value 7 or 0

B. A wire array with 7 elements each 8 bits wide

C. A wire that is 8 bits wide, from bit 7 down to bit 0

D. A wire that can only hold values 7 or 0

Solution

1. Step 1: Understand bus declaration syntax

   The syntax [7:0] means a vector from bit 7 down to bit 0, so 8 bits total.

2. Step 2: Interpret the declaration meaning

   Declaring wire [7:0] data_bus; creates a wire signal that is 8 bits wide, indexed 7 to 0.

3. Final Answer:

   A wire that is 8 bits wide, from bit 7 down to bit 0 -> Option C

4. Quick Check:

   Bit vector = 8 bits wide [OK]

Hint: Look for [msb:lsb] to find bus width quickly [OK]

Common Mistakes:

• Thinking it declares multiple wires instead of one bus
• Confusing bit range direction (7:0 vs 0:7)
• Assuming it declares a single bit wire

2. Which of the following is the correct way to declare a 16-bit register named reg16 in Verilog?

easy

A. reg [15:0] reg16;

B. reg [0:15] reg16;

C. reg16 reg [15:0];

D. reg reg16[15:0];

Solution

1. Step 1: Recall correct syntax for bus declaration

   In Verilog, the bus width is declared inside square brackets before the variable name, like reg [width] name;.

2. Step 2: Check each option

   The correct syntax is reg [15:0] reg16;. reg reg16[15:0]; uses array syntax incorrectly. reg16 reg [15:0]; has incorrect order of keywords. reg [0:15] reg16; uses a reversed bit range, which is allowed but less common and can cause confusion.

3. Final Answer:

   reg [15:0] reg16; -> Option A

4. Quick Check:

   Correct bus syntax = reg [msb:lsb] name [OK]

Hint: Bus width always goes inside [] before the name [OK]

Common Mistakes:

• Using array syntax instead of bus syntax
• Placing the bus range after the variable name
• Reversing the bit range incorrectly

3. Given the code snippet:

wire [3:0] bus;
assign bus = 4'b1010;
wire bit0 = bus[0];
wire bit3 = bus[3];

What are the values of bit0 and bit3 respectively?

medium

A. bit0 = 0, bit3 = 1

B. bit0 = 1, bit3 = 0

C. bit0 = 1, bit3 = 1

D. bit0 = 0, bit3 = 0

Solution

1. Step 1: Understand bit indexing in bus

   The bus is assigned 4'b1010, which means bit3=1, bit2=0, bit1=1, bit0=0 (MSB to LSB).

2. Step 2: Extract bit0 and bit3 values

   bit0 is the least significant bit, which is 0. bit3 is the most significant bit, which is 1.

3. Final Answer:

   bit0 = 0, bit3 = 1 -> Option A

4. Quick Check:

   bus[3:0] = 1010, bit0=0, bit3=1 [OK]

Hint: MSB is highest index, LSB is zero index [OK]

Common Mistakes:

• Confusing bit0 with MSB instead of LSB
• Reading bits in reverse order
• Misinterpreting binary literal order

4. Identify the error in the following Verilog declaration:

wire [7:0] data;
wire [7:0] data_bus;
assign data = data_bus[8];

medium

A. Missing semicolon after assign statement

B. Index 8 is out of range for data_bus

C. Cannot assign wire to wire

D. data_bus should be declared as reg

Solution

1. Step 1: Check bus range and indexing

   data_bus is declared as 8 bits wide with indices 7 down to 0, so valid indices are 0 to 7.

2. Step 2: Identify invalid index usage

   The code tries to access data_bus[8], which is outside the declared range, causing an error.

3. Final Answer:

   Index 8 is out of range for data_bus -> Option B

4. Quick Check:

   Bus index must be within declared range [OK]

Hint: Check index is within [msb:lsb] range [OK]

Common Mistakes:

• Using index equal to bus width instead of max index
• Thinking wire-to-wire assign is invalid
• Ignoring semicolon errors

5. You want to declare a 12-bit bus named control_signal where bit 11 is the most significant bit and bit 0 is the least significant bit. Which declaration is correct and why?

Options:
A) wire [11:0] control_signal;
B) wire [0:11] control_signal;
C) wire control_signal[11:0];
D) wire control_signal[0:11];

hard

A. wire control_signal[0:11]; because this declares an array with reversed indices

B. wire [0:11] control_signal; because LSB is first index

C. wire control_signal[11:0]; because this declares an array of wires

D. wire [11:0] control_signal; because MSB must be higher index first

Solution

1. Step 1: Understand bit vector direction

   In Verilog, the most common and recommended way is to declare buses with MSB first, e.g., [11:0], so bit 11 is MSB and bit 0 is LSB.

2. Step 2: Analyze each option

   wire [11:0] control_signal; because MSB must be higher index first correctly declares a 12-bit bus with MSB=11 and LSB=0. The options with wire control_signal[11:0]; and wire control_signal[0:11]; declare arrays, not buses. wire [0:11] control_signal; because LSB is first index reverses the range, which is legal but uncommon and can cause confusion.

3. Final Answer:

   wire [11:0] control_signal; because MSB must be higher index first -> Option D

4. Quick Check:

   MSB:LSB = [11:0] for 12-bit bus [OK]

Hint: Use [msb:lsb] with MSB > LSB for clarity [OK]

Common Mistakes:

• Confusing array declaration with bus declaration
• Using reversed bit range causing indexing confusion
• Assuming [0:11] is standard for MSB to LSB