Assign statement for continuous logic in Verilog - Mini Project: Build & Apply

Assign Statement for Continuous Logic in Verilog

📖 Scenario: You are designing a simple digital circuit that controls a light based on two switches. The light should turn on only when both switches are on.

🎯 Goal: Build a Verilog module using an assign statement to continuously set the output light signal based on the input switches.

📋 What You'll Learn

Create a module named LightControl with inputs switch1 and switch2 and output light

Use an assign statement to continuously set light to 1 only when both switch1 and switch2 are 1

Use only continuous assignment (no always blocks)

Print the value of light for given inputs in a testbench

💡 Why This Matters

🌍 Real World

Continuous assignment statements are used in hardware design to model combinational logic circuits that react instantly to input changes.

💼 Career

Understanding continuous assignments is essential for digital design engineers working with FPGAs or ASICs to implement logic circuits efficiently.

1

Create the module with inputs and output

Write a Verilog module named LightControl with inputs switch1 and switch2 and output light. Declare all ports as type wire.

Verilog

module LightControl(input wire switch1, input wire switch2, output wire light);
// Your code here
endmodule

Hint

Start by declaring the module and its ports exactly as specified.

2

Add the continuous assign statement

Inside the LightControl module, add an assign statement that sets light to the logical AND of switch1 and switch2.

Verilog

module LightControl(input wire switch1, input wire switch2, output wire light);
// Add assign statement here
endmodule

Hint

Use the assign keyword followed by the output and the expression.

3

Create a testbench module

Write a testbench module named TestLightControl that declares reg variables switch1 and switch2, and a wire light. Instantiate LightControl inside it.

Verilog

module LightControl(input wire switch1, input wire switch2, output wire light);
    assign light = switch1 & switch2;
endmodule

// Write testbench module here

Hint

Declare reg for inputs and wire for output. Instantiate the module with named port connections.

4

Add stimulus and display output

In the TestLightControl module, add an initial block that sets switch1 and switch2 to 0 and 1 in all combinations with 10 time unit delays. Use $display to print the values of switch1, switch2, and light after each change.

Verilog

module LightControl(input wire switch1, input wire switch2, output wire light);
    assign light = switch1 & switch2;
endmodule

module TestLightControl;
    reg switch1;
    reg switch2;
    wire light;

    LightControl uut(.switch1(switch1), .switch2(switch2), .light(light));

    // Add initial block with stimulus and display here
endmodule

Hint

Use an initial block with delays and $display to show the output for each input combination.

Practice

1.

What is the main purpose of the assign statement in Verilog?

easy

A. To declare a register variable

B. To continuously drive a wire with a logic expression

C. To create a clock signal

D. To define a module interface

Solution

1. Step 1: Understand the role of assign

   The assign statement is used to drive wires continuously with logic expressions.

2. Step 2: Differentiate from other statements

   It is not used for declaring registers, clocks, or module interfaces.

3. Final Answer:

   To continuously drive a wire with a logic expression -> Option B

4. Quick Check:

   assign drives wires continuously = B [OK]

Hint: Assign always drives wires with logic expressions [OK]

Common Mistakes:

• Confusing assign with register declaration
• Thinking assign creates clock signals
• Using assign inside always blocks

2.

Which of the following is the correct syntax for a continuous assignment in Verilog?

?

easy

A. assign out = a & b;

B. assign out := a & b;

C. assign out == a & b;

D. assign out => a & b;

Solution

1. Step 1: Recall correct assign syntax

   The correct syntax uses a single equals sign: assign out = expression;

2. Step 2: Check each option

   assign out = a & b; uses = correctly. Options B, C, and D use invalid operators for assignment.

3. Final Answer:

   assign out = a & b; -> Option A

4. Quick Check:

   Assign uses = for continuous assignment = A [OK]

Hint: Assign uses single =, not := or == [OK]

Common Mistakes:

• Using := like in other languages
• Using == which is comparison, not assignment
• Using => which is invalid here

3.

Given the code below, what is the value of out when a=1 and b=0?

wire a, b, out;
assign out = a | b;

medium

A. Z (high impedance)

B. 0

C. 1

D. X (unknown)

Solution

1. Step 1: Understand the assign expression

   The output out is assigned the OR of a and b.

2. Step 2: Calculate OR for given inputs

   With a=1 and b=0, 1 | 0 = 1.

3. Final Answer:

   1 -> Option C

4. Quick Check:

   1 OR 0 = 1 [OK]

Hint: OR of 1 and 0 is 1 [OK]

Common Mistakes:

• Confusing OR with AND operation
• Assuming output is unknown or high impedance
• Forgetting assign updates continuously

4.

Identify the error in the following Verilog code snippet:

wire a, b, out;
assign out = a & b

medium

A. Missing semicolon at the end of the assign statement

B. Incorrect use of wire keyword

C. Assign statement cannot use & operator

D. Output out should be declared as reg

Solution

1. Step 1: Check syntax of assign statement

   Every assign statement must end with a semicolon.

2. Step 2: Identify missing semicolon

   The code misses a semicolon after a & b, causing syntax error.

3. Final Answer:

   Missing semicolon at the end of the assign statement -> Option A

4. Quick Check:

   Assign statements require semicolon = C [OK]

Hint: Always end assign statements with semicolon [OK]

Common Mistakes:

• Omitting semicolon at end of assign
• Thinking out must be reg for assign
• Believing & operator is invalid in assign

5.

How would you use the assign statement to create a 2-input XOR gate output out from inputs a and b?

hard

A. assign out = ~(a ^ b);

B. assign out = a & b;

C. assign out = a | b;

D. assign out = a ^ b;

Solution

1. Step 1: Recall XOR operator in Verilog

   The XOR operator is ^ and produces 1 when inputs differ.

2. Step 2: Write assign statement for XOR

   Use assign out = a ^ b; to continuously assign XOR result.

3. Final Answer:

   assign out = a ^ b; -> Option D

4. Quick Check:

   XOR uses ^ operator = D [OK]

Hint: XOR operator is ^ in assign statements [OK]

Common Mistakes:

• Using & or | instead of ^ for XOR
• Negating XOR result mistakenly
• Trying to assign XOR inside always block only