Assign statement for continuous logic in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of continuous assignment with bitwise AND

What is the output of the following Verilog code snippet when a = 4'b1101 and b = 4'b1011?

Verilog

module test;
  reg [3:0] a = 4'b1101;
  reg [3:0] b = 4'b1011;
  wire [3:0] c;
  assign c = a & b;
  initial begin
    $display("c = %b", c);
  end
endmodule

A c = 1011

B c = 1111

C c = 1101

D c = 1001

💡 Hint

Remember bitwise AND compares each bit of a and b.

The bitwise AND of 1101 and 1011 is 1001 because only bits where both are 1 remain 1.

❓ Predict Output

intermediate

Continuous assignment with ternary operator

What will be the value of wire y after the following code runs with sel = 1, in1 = 1'b0, and in2 = 1'b1?

Verilog

module mux_test;
  reg sel = 1'b1;
  reg in1 = 1'b0;
  reg in2 = 1'b1;
  wire y;
  assign y = sel ? in2 : in1;
  initial begin
    $display("y = %b", y);
  end
endmodule

A y = 1

B y = 0

C y = x

D y = z

💡 Hint

The ternary operator chooses in2 when sel is 1.

Since sel is 1, y is assigned in2 which is 1.

🔧 Debug

advanced

Identify the error in continuous assignment

What error will this Verilog code produce?

Verilog

module error_test;
  reg a = 1'b1;
  wire b;
  assign b = a + 1'b1;
endmodule

A Width mismatch error: addition result wider than b

B No error, b will be 2'b10

C Type error: incompatible types in assign statement

D Syntax error: cannot add reg and wire directly

💡 Hint

Check the width of the result of addition compared to wire b.

Adding 1'b1 and 1'b1 results in 2 bits (2'b10), but b is only 1 bit wide, causing a width mismatch warning or error.

❓ Predict Output

advanced

Output of continuous assignment with concatenation

What is the output of wire z after this code runs with a = 2'b10 and b = 2'b01?

Verilog

module concat_test;
  reg [1:0] a = 2'b10;
  reg [1:0] b = 2'b01;
  wire [3:0] z;
  assign z = {a, b};
  initial begin
    $display("z = %b", z);
  end
endmodule

A z = 0110

B z = 1001

C z = 1010

D z = 0101

💡 Hint

Concatenation joins bits from left to right.

Concatenating a=10 and b=01 results in 1001.

❓ Predict Output

expert

Value of wire after continuous assignment with reduction operator

Given a = 4'b1011, what is the value of wire y after this code runs?

Verilog

module reduction_test;
  reg [3:0] a = 4'b1011;
  wire y;
  assign y = &a;
  initial begin
    $display("y = %b", y);
  end
endmodule

A y = 1

B y = z

C y = 0

D y = x

💡 Hint

The & operator reduces all bits by ANDing them together.

The bits of a are 1,0,1,1. ANDing all bits results in 0 because one bit is 0.

Practice

1.

What is the main purpose of the assign statement in Verilog?

easy

A. To declare a register variable

B. To continuously drive a wire with a logic expression

C. To create a clock signal

D. To define a module interface

Solution

1. Step 1: Understand the role of assign

   The assign statement is used to drive wires continuously with logic expressions.

2. Step 2: Differentiate from other statements

   It is not used for declaring registers, clocks, or module interfaces.

3. Final Answer:

   To continuously drive a wire with a logic expression -> Option B

4. Quick Check:

   assign drives wires continuously = B [OK]

Hint: Assign always drives wires with logic expressions [OK]

Common Mistakes:

• Confusing assign with register declaration
• Thinking assign creates clock signals
• Using assign inside always blocks

2.

Which of the following is the correct syntax for a continuous assignment in Verilog?

?

easy

A. assign out = a & b;

B. assign out := a & b;

C. assign out == a & b;

D. assign out => a & b;

Solution

1. Step 1: Recall correct assign syntax

   The correct syntax uses a single equals sign: assign out = expression;

2. Step 2: Check each option

   assign out = a & b; uses = correctly. Options B, C, and D use invalid operators for assignment.

3. Final Answer:

   assign out = a & b; -> Option A

4. Quick Check:

   Assign uses = for continuous assignment = A [OK]

Hint: Assign uses single =, not := or == [OK]

Common Mistakes:

• Using := like in other languages
• Using == which is comparison, not assignment
• Using => which is invalid here

3.

Given the code below, what is the value of out when a=1 and b=0?

wire a, b, out;
assign out = a | b;

medium

A. Z (high impedance)

B. 0

C. 1

D. X (unknown)

Solution

1. Step 1: Understand the assign expression

   The output out is assigned the OR of a and b.

2. Step 2: Calculate OR for given inputs

   With a=1 and b=0, 1 | 0 = 1.

3. Final Answer:

   1 -> Option C

4. Quick Check:

   1 OR 0 = 1 [OK]

Hint: OR of 1 and 0 is 1 [OK]

Common Mistakes:

• Confusing OR with AND operation
• Assuming output is unknown or high impedance
• Forgetting assign updates continuously

4.

Identify the error in the following Verilog code snippet:

wire a, b, out;
assign out = a & b

medium

A. Missing semicolon at the end of the assign statement

B. Incorrect use of wire keyword

C. Assign statement cannot use & operator

D. Output out should be declared as reg

Solution

1. Step 1: Check syntax of assign statement

   Every assign statement must end with a semicolon.

2. Step 2: Identify missing semicolon

   The code misses a semicolon after a & b, causing syntax error.

3. Final Answer:

   Missing semicolon at the end of the assign statement -> Option A

4. Quick Check:

   Assign statements require semicolon = C [OK]

Hint: Always end assign statements with semicolon [OK]

Common Mistakes:

• Omitting semicolon at end of assign
• Thinking out must be reg for assign
• Believing & operator is invalid in assign

5.

How would you use the assign statement to create a 2-input XOR gate output out from inputs a and b?

hard

A. assign out = ~(a ^ b);

B. assign out = a & b;

C. assign out = a | b;

D. assign out = a ^ b;

Solution

1. Step 1: Recall XOR operator in Verilog

   The XOR operator is ^ and produces 1 when inputs differ.

2. Step 2: Write assign statement for XOR

   Use assign out = a ^ b; to continuously assign XOR result.

3. Final Answer:

   assign out = a ^ b; -> Option D

4. Quick Check:

   XOR uses ^ operator = D [OK]

Hint: XOR operator is ^ in assign statements [OK]

Common Mistakes:

• Using & or | instead of ^ for XOR
• Negating XOR result mistakenly
• Trying to assign XOR inside always block only