Synthesis warnings and how to fix them in Verilog - Step-by-Step Execution

Concept Flow - Synthesis warnings and how to fix them

Write Verilog code

↓

Run synthesis tool

↓

Check synthesis warnings

↓

Identify warning type

↓

Apply fix to code

↓

Re-run synthesis

↓

Warnings cleared?

No→Repeat fix

Yes↓

Code ready for implementation

This flow shows how you write Verilog code, run synthesis, check warnings, fix them, and repeat until no warnings remain.

Execution Sample

Verilog

module example(input clk, input rst, output reg q);
  always @(posedge clk) begin
    if (rst) q <= 0;
  end
endmodule

This code has a synthesis warning because 'q' is not assigned in all conditions inside the always block.

Execution Table

Step	Code Line	Warning Detected	Cause	Fix Applied
1	always @(posedge clk) begin if (rst) q <= 0; end	Incomplete assignment warning	'q' not assigned when rst=0	Add else branch to assign 'q'
2	always @(posedge clk) begin if (rst) q <= 0; else q <= q; end	Warning cleared	All conditions assign 'q'	No fix needed
3	End of synthesis	No warnings	Code is synthesizable	Ready for implementation

💡 No synthesis warnings remain after fixes

Variable Tracker

Variable	Start	After Fix 1	Final
q	undefined	assigned every clock cycle	assigned every clock cycle

Key Moments - 2 Insights

Why does the synthesis tool warn about incomplete assignments?

Because in the first always block (see step 1 in execution_table), 'q' is assigned only when rst=1, leaving it undefined otherwise, which can cause latch inference.

How does adding an else branch fix the warning?

Adding else assigns 'q' in all cases (step 2), preventing unintended latches and making the design fully synchronous.

Visual Quiz - 3 Questions

Look at the execution table, what warning appears at step 1?

A Incomplete assignment warning

B Syntax error

C No warning

D Timing violation

💡 Hint

Check the 'Warning Detected' column in step 1 of the execution_table

At which step does the warning get cleared?

A Step 1

B Step 2

C Step 3

D Never

💡 Hint

Look at the 'Warning Detected' column for 'Warning cleared' in the execution_table

If we remove the else branch fix, what would happen to variable 'q' in variable_tracker?

A 'q' would be assigned every clock cycle

B 'q' would cause a syntax error

C 'q' would remain undefined sometimes

D 'q' would be optimized away

💡 Hint

See variable_tracker row for 'q' showing assignment changes after fix

Concept Snapshot

Synthesis warnings occur when code is incomplete or ambiguous.
Common warning: incomplete assignments causing latches.
Fix by assigning all outputs in every condition.
Add else branches in always blocks.
Re-run synthesis until warnings clear.
Clean code ensures reliable hardware.

Full Transcript

This visual execution shows how synthesis warnings appear when Verilog code is incomplete, such as missing assignments in some conditions. The example code assigns output 'q' only when reset is active, causing a warning about incomplete assignments. Adding an else branch assigns 'q' in all cases, fixing the warning. The execution table traces these steps, showing the warning at step 1 and its clearance at step 2. The variable tracker shows how 'q' changes from undefined to fully assigned. Key moments explain why incomplete assignments cause warnings and how else branches fix them. The quiz tests understanding of warning detection and fixes. The snapshot summarizes how to handle synthesis warnings by ensuring all outputs are assigned in every condition to avoid latches and synthesis issues.

Practice

1. What is the main reason synthesis tools generate warnings about incomplete case statements in Verilog?

easy

A. Because the case statement is inside an always block.

B. Because the syntax of the case statement is incorrect.

C. Because the tool does not support case statements.

D. Because not all possible input cases are covered, which may cause unintended hardware behavior.

Solution

1. Step 1: Understand synthesis warnings for case statements

   Synthesis tools warn when a case statement does not cover all possible input values, which can cause unintended latches or hardware behavior.

2. Step 2: Reason why incomplete coverage is problematic

   If some input values are not handled, the hardware may hold previous values or behave unpredictably, which is why the tool warns.

3. Final Answer:

   Because not all possible input cases are covered, which may cause unintended hardware behavior. -> Option D

4. Quick Check:

   Incomplete case coverage = synthesis warning [OK]

Hint: Always cover all input cases in case to avoid warnings [OK]

Common Mistakes:

• Thinking syntax errors cause incomplete case warnings
• Ignoring default cases in case statements
• Assuming tools don't check for all input values

2. Which of the following Verilog code snippets will NOT cause a synthesis warning about unassigned signals?

easy

A. module example(input clk, input a, output reg q); always @(posedge clk) q <= a; endmodule

B. module example(input clk, input a, output reg q); always @(posedge clk) ; endmodule

C. module example(input clk, input a, output reg q); reg temp; always @(posedge clk) temp <= a; endmodule

D. module example(input clk, input a, output reg q); reg temp; always @(posedge clk) q <= temp; endmodule

Solution

1. Step 1: Identify unassigned signals in each snippet

   module example(input clk, input a, output reg q); always @(posedge clk) q <= a; endmodule assigns q on clock edge, so no unassigned output. module example(input clk, input a, output reg q); always @(posedge clk) ; endmodule has an empty always block, so q is never assigned. module example(input clk, input a, output reg q); reg temp; always @(posedge clk) temp <= a; endmodule assigns temp but q is unassigned output. module example(input clk, input a, output reg q); reg temp; always @(posedge clk) q <= temp; endmodule assigns q from temp, but temp is never assigned.

2. Step 2: Determine which code avoids unassigned signals

   Only module example(input clk, input a, output reg q); always @(posedge clk) q <= a; endmodule properly assigns the output q and has no unassigned signals, so no synthesis warning.

3. Final Answer:

   module example(input clk, input a, output reg q); always @(posedge clk) q <= a; endmodule -> Option A

4. Quick Check:

   All outputs assigned = no warnings [OK]

Hint: Check if all outputs get assigned in every clock cycle [OK]

Common Mistakes:

• Ignoring that outputs must be assigned to avoid warnings
• Assuming internal regs cause warnings if unassigned
• Confusing blocking and non-blocking assignments

3. Given the following Verilog code, what synthesis warning will most likely appear?

module test(input wire [1:0] sel, output reg out);
  always @(*) begin
    case(sel)
      2'b00: out = 1'b0;
      2'b01: out = 1'b1;
      // Missing cases for 2'b10 and 2'b11
    endcase
  end
endmodule

medium

A. Warning about incomplete case statement causing inferred latch.

B. Warning about unused input sel.

C. Warning about multiple drivers for out.

D. No warnings; code is synthesizable as is.

Solution

1. Step 1: Analyze the case statement coverage

   The case covers only 2 of 4 possible values of sel. Missing 2'b10 and 2'b11 cases.

2. Step 2: Understand synthesis implications of missing cases

   Because not all cases are covered and no default is provided, synthesis infers a latch to hold out value for missing cases, causing a warning.

3. Final Answer:

   Warning about incomplete case statement causing inferred latch. -> Option A

4. Quick Check:

   Incomplete case = inferred latch warning [OK]

Hint: Add default case to avoid inferred latch warnings [OK]

Common Mistakes:

• Assuming no warning if some cases are missing
• Confusing unused input warnings with case coverage
• Ignoring latch inference from incomplete cases

4. Identify the synthesis warning and fix in the following Verilog snippet:

module fixme(input clk, input a, output reg q);
  reg temp;
  always @(posedge clk) begin
    temp <= a;
  end
  always @(posedge clk) begin
    q <= temp;
  end
endmodule

medium

A. Warning: Unused signal temp. Fix: Remove temp and assign q directly.

B. No synthesis warnings; code is correct.

C. Warning: temp is assigned but never used. Fix: Connect temp to output.

D. Warning: Multiple drivers for q. Fix: Use only one always block for q.

Solution

1. Step 1: Check signal usage and assignments

   temp is assigned from a on clock edge, then q is assigned from temp on next clock edge. Both signals are used properly.

2. Step 2: Verify if multiple drivers or unused signals exist

   Only one always block drives temp, and one drives q. No multiple drivers or unused signals.

3. Final Answer:

   No synthesis warnings; code is correct. -> Option B

4. Quick Check:

   All signals assigned and used properly = no warnings [OK]

Hint: Check if every assigned signal is used and driven once [OK]

Common Mistakes:

• Assuming temp is unused because it is intermediate
• Thinking multiple always blocks cause multiple drivers if signals differ
• Ignoring proper signal flow over clock cycles

5. You have a combinational always block with multiple outputs, but synthesis warns about inferred latches. How can you fix this warning effectively?

hard

A. Add more inputs to the sensitivity list of the always block.

B. Remove the always block and use continuous assignments instead.

C. Add a default assignment to all outputs at the start of the always block.

D. Declare all outputs as wires instead of regs.

Solution

1. Step 1: Understand why inferred latches occur in combinational blocks

   If outputs are not assigned in all possible paths, synthesis infers latches to hold previous values, causing warnings.

2. Step 2: Fix by adding default assignments

   Assign default values to all outputs at the start of the always block to ensure they are always driven, preventing latch inference.

3. Final Answer:

   Add a default assignment to all outputs at the start of the always block. -> Option C

4. Quick Check:

   Default assignments prevent inferred latches [OK]

Hint: Initialize outputs at block start to avoid latches [OK]

Common Mistakes:

• Thinking sensitivity list affects latch warnings
• Assuming changing output type fixes latch inference
• Removing always block without replacing logic