Generate statement for repetitive structures in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog generate block?

Consider the following Verilog code snippet using a generate statement. What will be the value of the wire array out after simulation?

module gen_example(output wire [3:0] out);
  genvar i;
  generate
    for (i = 0; i < 4; i = i + 1) begin : gen_loop
      assign out[i] = (i % 2 == 0) ? 1'b1 : 1'b0;
    end
  endgenerate
endmodule

Verilog

module gen_example(output wire [3:0] out);
  genvar i;
  generate
    for (i = 0; i < 4; i = i + 1) begin : gen_loop
      assign out[i] = (i % 2 == 0) ? 1'b1 : 1'b0;
    end
  endgenerate
endmodule

A out = 4'b1010

B out = 4'b0000

C out = 4'b1111

D out = 4'b0101

💡 Hint

Remember that the index i starts at 0 and increments by 1. The ternary operator assigns 1 when i is even.

The generate loop assigns 1 to out[i] when i is even (0 and 2), and 0 when i is odd (1 and 3). So out[0] = 1, out[1] = 0, out[2] = 1, out[3] = 0, which is 4'b1010 in binary. Verilog bit ordering means out[3] is the most significant bit, so the vector is 4'b1010.

❓ Predict Output

intermediate

How many instances are created by this generate block?

Given the following Verilog code, how many instances of the module bit_cell are created?

module top_module();
  genvar idx;
  generate
    for (idx = 0; idx < 8; idx = idx + 2) begin : gen_cells
      bit_cell cell_inst();
    end
  endgenerate
endmodule

module bit_cell();
  // Some internal logic
endmodule

Verilog

module top_module();
  genvar idx;
  generate
    for (idx = 0; idx < 8; idx = idx + 2) begin : gen_cells
      bit_cell cell_inst();
    end
  endgenerate
endmodule

module bit_cell();
  // Some internal logic
endmodule

A 8 instances

B 4 instances

C 2 instances

D 16 instances

💡 Hint

Count how many times the loop runs with the given step size.

The loop variable idx starts at 0 and increments by 2 until it is less than 8. The values are 0, 2, 4, 6, so 4 iterations and thus 4 instances of bit_cell are created.

🔧 Debug

advanced

Identify the error in this generate block

Examine the following Verilog code. What error will occur during compilation?

module error_gen();
  genvar i;
  generate
    for (i = 0; i < 3; i = i + 1) begin
      wire [3:0] temp;
      assign temp = i + 1;
    end
  endgenerate
endmodule

Verilog

module error_gen();
  genvar i;
  generate
    for (i = 0; i < 3; i = i + 1) begin
      wire [3:0] temp;
      assign temp = i + 1;
    end
  endgenerate
endmodule

A Multiple drivers error: 'temp' declared multiple times without unique names

B No error, code compiles successfully

C Syntax error: 'assign' cannot be used with a wire declared inside generate block

D Type error: cannot assign integer to wire

💡 Hint

Consider how generate blocks create multiple instances and how signals must be uniquely named.

The wire 'temp' is declared inside the generate loop without unique names for each instance. This causes multiple declarations of 'temp' in the same scope, leading to multiple drivers error.

📝 Syntax

advanced

Which option shows the correct syntax for a generate-if statement?

Select the option that correctly uses a generate-if statement in Verilog to conditionally instantiate a module.

A

generate
  if (ENABLE) {
    my_module inst();
  }
endgenerate

B

generate
  if ENABLE then
    my_module inst();
  end
endgenerate

C

generate
  if ENABLE {
    my_module inst();
  }
endgenerate

D

generate
  if (ENABLE) begin
    my_module inst();
  end
endgenerate

💡 Hint

Remember Verilog uses parentheses for conditions and 'begin-end' blocks.

Option D uses correct Verilog syntax: 'if (condition) begin ... end'. Options B, C, and D use incorrect syntax such as missing parentheses, 'then' keyword, or braces which are not valid in Verilog.

🚀 Application

expert

How to generate a parameterized bus with alternating bits using generate?

You want to create a parameterized Verilog module that outputs a bus of width WIDTH where bits alternate between 1 and 0 starting with 1 at bit 0. Which generate block correctly implements this?

Assume parameter WIDTH = 8;

Verilog

module alt_bus #(parameter WIDTH = 8) (output wire [WIDTH-1:0] bus_out);
  genvar i;
  generate
    for (i = 0; i < WIDTH; i = i + 1) begin : gen_alt
      // Fill in the assignment here
    end
  endgenerate
endmodule

A assign bus_out[i] = (i & 1) ? 1'b1 : 1'b0;

B assign bus_out[i] = (i % 2 == 1) ? 1'b1 : 1'b0;

C assign bus_out[i] = (i % 2 == 0) ? 1'b1 : 1'b0;

D assign bus_out[i] = (i & 1) ? 1'b0 : 1'b1;

💡 Hint

Bit 0 should be 1, so check which condition makes bit 0 equal to 1.

Option C assigns 1 to even bits (i=0,2,4...) and 0 to odd bits, matching the requirement that bit 0 is 1 and bits alternate. Option C assigns 1 to odd bits, so bit 0 would be 0. Option C and D invert the pattern incorrectly.

Practice

1. What is the main purpose of the generate statement in Verilog?

easy

A. To assign values to wires

B. To declare variables inside a module

C. To define input and output ports

D. To create multiple instances of hardware blocks using loops

Solution

1. Step 1: Understand the generate statement role

   The generate statement is used to repeat hardware blocks multiple times using loops.

2. Step 2: Compare with other options

   Declaring variables, defining ports, and assigning wires are unrelated to generate's purpose.

3. Final Answer:

   To create multiple instances of hardware blocks using loops -> Option D

4. Quick Check:

   Generate repeats blocks = D [OK]

Hint: Generate repeats hardware blocks with loops [OK]

Common Mistakes:

• Confusing generate with variable declaration
• Thinking generate defines ports
• Using generate for simple assignments

2. Which of the following is the correct syntax to declare a generate loop variable in Verilog?

easy

A. genvar i;\ngenerate\n for (i=0; i<4; i=i+1) begin ... end\nendgenerate

B. int i;

C. genvar i;\nbegin\n for (i=0; i<4; i=i+1) begin ... end\nendgenerate

D. var i;\ngenerate\n for (i=0; i<4; i=i+1) begin ... end\nendgenerate"

Solution

1. Step 1: Identify correct genvar declaration and generate block

   In Verilog, genvar declares the loop variable, and the generate block wraps the for loop.

2. Step 2: Check syntax correctness

   genvar i;\ngenerate\n for (i=0; i<4; i=i+1) begin ... end\nendgenerate correctly uses genvar i; and generate ... endgenerate with a for loop.

3. Final Answer:

   genvar i; generate for (i=0; i<4; i=i+1) begin ... end endgenerate -> Option A

4. Quick Check:

   genvar + generate block = B [OK]

Hint: Use genvar with generate and for loop [OK]

Common Mistakes:

• Using int or var instead of genvar
• Omitting generate/endgenerate keywords
• Placing begin without generate

3. What will be the output of the following Verilog generate code snippet?

genvar i;
generate
  for (i=0; i<3; i=i+1) begin : gen_block
    wire [3:0] w = i + 1;
  end
endgenerate

How many wires named w are created and what are their values?

medium

A. 3 wires named w with values 0, 1, and 2

B. Syntax error due to wire initialization inside generate

C. 3 wires named w with values 1, 2, and 3

D. 1 wire named w with value 3

Solution

1. Step 1: Count generated instances

   The for loop runs 3 times (i=0,1,2), creating 3 separate blocks each with a wire named w.

2. Step 2: Determine wire values

   Wire declarations cannot be initialized directly inside generate blocks in Verilog; this causes a syntax error.

3. Final Answer:

   Syntax error due to wire initialization inside generate -> Option B

4. Quick Check:

   Wire initialization inside generate is invalid [OK]

Hint: Wire declarations inside generate cannot have initializations [OK]

Common Mistakes:

• Thinking only one wire is created
• Confusing values as starting from 0
• Assuming wire initialization is allowed inside generate

4. Identify the error in this Verilog generate block:

genvar i;
generate
  for (i=0; i<=3; i=i+1) begin
    wire w[i];
  end
endgenerate

medium

A. Cannot use variable index in wire declaration inside generate

B. genvar must be declared inside the generate block

C. The loop condition should be < instead of <=

D. Missing endgenerate keyword

Solution

1. Step 1: Analyze wire declaration with variable index

   Verilog does not allow variable indices like w[i] in wire declarations inside generate loops.

2. Step 2: Check other syntax elements

   genvar can be declared outside generate, loop condition <= is valid, and endgenerate is present.

3. Final Answer:

   Cannot use variable index in wire declaration inside generate -> Option A

4. Quick Check:

   Variable index in wire declaration is invalid [OK]

Hint: Wire sizes must be constant, not variable expressions [OK]

Common Mistakes:

• Thinking loop condition <= is wrong
• Assuming genvar must be inside generate
• Forgetting endgenerate keyword

5. You want to create 4 instances of a module my_block with parameter INDEX set to the loop index. Which generate code correctly achieves this?

hard

A. genvar i;
generate
for (i=0; i<4; i=i+1) begin
my_block #(.INDEX(i)) inst();
end
endgenerate

B. genvar i;
generate
for (i=1; i<=4; i=i+1) begin : gen_loop
my_block #(.INDEX(i)) inst();
end
endgenerate

C. genvar i;
generate
for (i=0; i<4; i=i+1) begin : gen_loop
my_block #(.INDEX(i)) inst();
end
endgenerate

D. genvar i;
for (i=0; i<4; i=i+1) begin : gen_loop
my_block #(.INDEX(i)) inst();
end

Solution

1. Step 1: Check loop range and generate block

   genvar i; generate for (i=0; i<4; i=i+1) begin : gen_loop my_block #(.INDEX(i)) inst(); end endgenerate uses i=0; i<4 which creates 4 instances with indices 0 to 3 inside a generate block.

2. Step 2: Verify instance naming and parameter passing

   genvar i; generate for (i=0; i<4; i=i+1) begin : gen_loop my_block #(.INDEX(i)) inst(); end endgenerate uses a named generate block gen_loop and passes INDEX(i) correctly to each instance.

3. Final Answer:

   genvar i; generate for (i=0; i<4; i=i+1) begin : gen_loop my_block #(.INDEX(i)) inst(); end endgenerate -> Option C

4. Quick Check:

   Generate with genvar, named block, and parameter = A [OK]

Hint: Use named generate blocks and genvar for parameters [OK]

Common Mistakes:

• Starting loop at 1 instead of 0
• Missing named generate block
• Omitting generate/endgenerate keywords