Why combinational logic is the foundation in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to define a simple AND gate module.

Verilog

module and_gate(input a, input b, output y);
  assign y = a [1] b;
endmodule

Drag options to blanks, or click blank then click option'

A&

B~

C^

D|

Attempts:

3 left

💡 Hint

Common Mistakes

Using | instead of & for AND operation.

The AND operation in Verilog is represented by the & operator.

2fill in blank

medium

Complete the code to define a combinational logic block using always block.

Verilog

module comb_logic(input a, input b, output reg y);
  always @(*) begin
    y = a [1] b;
  end
endmodule

Drag options to blanks, or click blank then click option'

A&

B^

C|

D~

Attempts:

3 left

💡 Hint

Common Mistakes

Using & instead of | for OR operation.

The OR operation uses the | operator in Verilog.

3fill in blank

hard

Fix the error in the combinational logic expression to output XOR of inputs.

Verilog

module xor_gate(input a, input b, output y);
  assign y = a [1] b;
endmodule

Drag options to blanks, or click blank then click option'

A|

B^

C&

D~

Attempts:

3 left

💡 Hint

Common Mistakes

Using & or | instead of ^ for XOR operation.

The XOR operation is represented by the ^ operator in Verilog.

4fill in blank

hard

Fill both blanks to create a combinational logic expression for (a AND b) OR c.

Verilog

module comb_expr(input a, input b, input c, output y);
  assign y = (a [1] b) [2] c;
endmodule

Drag options to blanks, or click blank then click option'

A&

B|

C^

D~

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping AND and OR operators.

The expression uses AND (&) first, then OR (|) to combine with c.

5fill in blank

hard

Fill all three blanks to create a combinational logic expression for (a XOR b) AND (NOT c).

Verilog

module complex_logic(input a, input b, input c, output y);
  assign y = (a [1] b) [2] ([3] c);
endmodule

Drag options to blanks, or click blank then click option'

A&

B|

C^

D~

Attempts:

3 left

💡 Hint

Common Mistakes

Using | instead of & for AND.

Using & instead of ^ for XOR.

Forgetting ~ for NOT.

XOR is ^, AND is &, and NOT is ~ in Verilog.

Practice

1. Why is combinational logic considered the foundation in digital design using Verilog?

easy

A. Because it stores data over time like memory elements.

B. Because its outputs depend only on current inputs, making it predictable and simple.

C. Because it requires clock signals to operate correctly.

D. Because it is only used for testing purposes.

Solution

1. Step 1: Understand the nature of combinational logic

   Combinational logic outputs depend solely on the current inputs without memory or delay.

2. Step 2: Compare with other logic types

   Sequential logic depends on past inputs and clock signals, unlike combinational logic.

3. Final Answer:

   Because its outputs depend only on current inputs, making it predictable and simple. -> Option B

4. Quick Check:

   Combinational logic = output depends only on current inputs [OK]

Hint: Combinational logic has no memory, only current inputs matter [OK]

Common Mistakes:

• Confusing combinational logic with sequential logic
• Thinking clock signals are needed for combinational logic
• Assuming combinational logic stores data

2. Which of the following is the correct way to define combinational logic in Verilog?

easy

A. assign out = in1 & in2;

B. always @(negedge clk) out <= in1 ^ in2;

C. initial begin out = in1 | in2; end

D. always @(posedge clk) begin out = in1 & in2; end

Solution

1. Step 1: Identify combinational logic syntax in Verilog

   Combinational logic is defined using continuous assignment with the assign keyword.

2. Step 2: Analyze each option

   Options A and B use clock edges, indicating sequential logic. initial begin out = in1 | in2; end uses initial, which is for simulation setup, not combinational logic.

3. Final Answer:

   assign out = in1 & in2; -> Option A

4. Quick Check:

   Combinational logic uses assign statements [OK]

Hint: Use 'assign' for combinational logic, not always blocks with clocks [OK]

Common Mistakes:

• Using always blocks with clock edges for combinational logic
• Confusing initial blocks with combinational logic
• Using non-continuous assignments for combinational logic

3. What is the output of the following Verilog code snippet?

module test(input wire a, b, output wire y);
  assign y = a & b;
endmodule

If a = 1 and b = 0, what is y?

medium

A. Z (high impedance)

B. 1

C. 0

D. X (unknown)

Solution

1. Step 1: Understand the logic operation

   The output y is assigned the AND of inputs a and b.

2. Step 2: Calculate the AND result for given inputs

   Given a = 1 and b = 0, the AND operation yields 0.

3. Final Answer:

   0 -> Option C

4. Quick Check:

   1 AND 0 = 0 [OK]

Hint: AND gate outputs 1 only if both inputs are 1 [OK]

Common Mistakes:

• Assuming output is 1 when one input is 1
• Confusing AND with OR operation
• Misreading input values

4. Identify the error in this Verilog code that tries to implement combinational logic:

module comb_logic(input wire x, y, output reg z);
  always @(x or y) begin
    z = x & y;
  end
endmodule

medium

A. The output should be declared as wire and use assign instead.

B. Using reg type for output in combinational logic is incorrect.

C. The sensitivity list should use * instead of x or y.

D. The always block should be triggered on clock edges.

Solution

1. Step 1: Understand output declaration for combinational logic

   Combinational logic outputs are usually declared as wire and assigned using assign.

2. Step 2: Analyze the code style

   The code uses reg and an always block, which is more typical for sequential or complex combinational logic but not the simplest form.

3. Step 3: Identify the best practice

   For simple combinational logic, use wire and assign to avoid unnecessary complexity.

4. Final Answer:

   The output should be declared as wire and use assign instead. -> Option A

5. Quick Check:

   Simple combinational logic uses wire and assign [OK]

Hint: Use wire and assign for simple combinational outputs [OK]

Common Mistakes:

• Thinking reg is always needed for outputs
• Confusing sensitivity list syntax
• Assuming always blocks require clock edges

5. You want to design a 2-to-1 multiplexer using combinational logic in Verilog. Which approach best uses combinational logic principles?

hard

A. Use an always block triggered by clock edges to assign output based on inputs.

B. Use initial blocks to set output values at the start of simulation.

C. Use a flip-flop to store the selected input and update output on clock.

D. Use continuous assignment with the ternary operator: assign out = sel ? in1 : in0;.

Solution

1. Step 1: Recall combinational logic characteristics

   Combinational logic outputs depend only on current inputs without clock or memory.

2. Step 2: Evaluate each option

   Use continuous assignment with the ternary operator: assign out = sel ? in1 : in0;. uses continuous assignment with a ternary operator, which is a classic combinational logic style. Options A and D use clocked logic (sequential). Use initial blocks to set output values at the start of simulation. is for simulation setup, not hardware logic.

3. Final Answer:

   Use continuous assignment with the ternary operator: assign out = sel ? in1 : in0;. -> Option D

4. Quick Check:

   Multiplexer combinational logic uses assign with ternary operator [OK]

Hint: Multiplexers use assign with ? : for combinational logic [OK]

Common Mistakes:

• Using clocked always blocks for combinational logic
• Confusing initial blocks with hardware logic
• Using flip-flops unnecessarily for combinational circuits