Operator precedence in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog expression?

Consider the following Verilog code snippet:

module test;
  initial begin
    int a = 2, b = 3, c = 4;
    int result = a + b * c;
    $display("%0d", result);
  end
endmodule

What value will be printed?

Verilog

module test;
  initial begin
    int a = 2, b = 3, c = 4;
    int result = a + b * c;
    $display("%0d", result);
  end
endmodule

A 9

B 20

C 24

D 14

💡 Hint

Remember the order of operations: multiplication happens before addition.

Multiplication (*) has higher precedence than addition (+). So, b * c = 3 * 4 = 12, then a + 12 = 14.

❓ Predict Output

intermediate

Evaluate this Verilog expression with parentheses

What is the output of this Verilog code?

module test;
  initial begin
    int x = 5, y = 2, z = 3;
    int val = (x + y) * z;
    $display("%0d", val);
  end
endmodule

Verilog

module test;
  initial begin
    int x = 5, y = 2, z = 3;
    int val = (x + y) * z;
    $display("%0d", val);
  end
endmodule

A 21

B 11

C 16

D 10

💡 Hint

Parentheses change the order of evaluation.

Parentheses force addition first: (5 + 2) = 7, then multiply by 3 = 21.

❓ Predict Output

advanced

What is the output of this mixed operator expression?

Analyze this Verilog code and determine the output:

module test;
  initial begin
    int a = 4, b = 2, c = 3;
    int res = a << b + c;
    $display("%0d", res);
  end
endmodule

Note: '+' and '<<' operators are used without parentheses.

Verilog

module test;
  initial begin
    int a = 4, b = 2, c = 3;
    int res = a << b + c;
    $display("%0d", res);
  end
endmodule

A 256

B 128

C 32

D 64

💡 Hint

Check operator precedence: '+' has higher precedence than '<<'.

In Verilog, the + operator has higher precedence than <<. So, b + c = 2 + 3 = 5, then a << 5 = 4 << 5 = 128.

❓ Predict Output

advanced

Determine the output of this expression with bitwise and logical operators

What will this Verilog code print?

module test;
  initial begin
    int a = 1, b = 0, c = 1;
    int result = a & b | c;
    $display("%0d", result);
  end
endmodule

Verilog

module test;
  initial begin
    int a = 1, b = 0, c = 1;
    int result = a & b | c;
    $display("%0d", result);
  end
endmodule

A 1

B 0

C 3

D 2

💡 Hint

Bitwise AND (&) has higher precedence than bitwise OR (|).

Bitwise AND (&) has higher precedence than bitwise OR (|). Compute a & b = 1 & 0 = 0, then 0 | c = 0 | 1 = 1.

❓ Predict Output

expert

What is the output of this complex expression with multiple operators?

Analyze this Verilog code snippet and find the output:

module test;
  initial begin
    int a = 3, b = 4, c = 2, d = 1;
    int val = a + b << c - d;
    $display("%0d", val);
  end
endmodule

Note: No parentheses are used.

Verilog

module test;
  initial begin
    int a = 3, b = 4, c = 2, d = 1;
    int val = a + b << c - d;
    $display("%0d", val);
  end
endmodule

A 28

B 35

C 14

D 7

💡 Hint

+ and - have higher precedence than << and associate left-to-right.

In Verilog, binary + and - have higher precedence than << and are left-associative. The expression is parsed as (a + b) << (c - d) = (3 + 4) << (2 - 1) = 7 << 1 = 14.

Practice

1. In Verilog, which operator has the highest precedence among the following?

easy

A. Addition (+)

B. Logical AND (&&)

C. Multiplication (*)

D. Bitwise OR (|)

Solution

1. Step 1: Understand operator categories

   Multiplication (*) is an arithmetic operator, addition (+) is also arithmetic but lower precedence than multiplication. Logical AND (&&) and bitwise OR (|) are logical and bitwise operators with lower precedence.

2. Step 2: Compare precedence levels

   Multiplication (*) has higher precedence than addition (+), logical AND (&&), and bitwise OR (|) in Verilog.

3. Final Answer:

   Multiplication (*) -> Option C

4. Quick Check:

   Multiplication > Addition > Logical AND > Bitwise OR [OK]

Hint: Arithmetic * has higher precedence than +, &&, | [OK]

Common Mistakes:

• Confusing logical AND (&&) precedence with arithmetic operators
• Assuming addition (+) has higher precedence than multiplication (*)
• Mixing bitwise OR (|) precedence with logical operators

2. Which of the following Verilog expressions correctly uses parentheses to ensure addition happens before multiplication?

easy

A. (a + b) * c

B. a + (b * c)

C. a + b * c

D. a * b + c

Solution

1. Step 1: Identify operator precedence

   Multiplication (*) has higher precedence than addition (+), so without parentheses, multiplication happens first.

2. Step 2: Check parentheses effect

   Only (a + b) * c forces addition before multiplication, changing the natural order.

3. Final Answer:

   (a + b) * c -> Option A

4. Quick Check:

   Parentheses override precedence to add first [OK]

Hint: Use parentheses to force addition before multiplication [OK]

Common Mistakes:

• Ignoring parentheses and assuming left-to-right evaluation
• Choosing expressions without parentheses that do not change precedence
• Confusing multiplication and addition order

3. Given the Verilog code snippet:

reg [3:0] a = 4; reg [3:0] b = 2; reg [3:0] c = 1; wire [3:0] result = a + b * c;

What is the value of result?

medium

A. Syntax error

B. 8

C. 3

D. 6

Solution

1. Step 1: Apply operator precedence

   Multiplication (*) has higher precedence than addition (+), so calculate b * c first: 2 * 1 = 2.

2. Step 2: Calculate addition

   Add a + (b * c): 4 + 2 = 6.

3. Final Answer:

   6 -> Option D

4. Quick Check:

   4 + (2 * 1) = 6 [OK]

Hint: Multiply before adding unless parentheses change order [OK]

Common Mistakes:

• Adding a + b first ignoring precedence
• Assuming syntax error due to reg and wire usage
• Confusing bit widths affecting calculation

4. Identify the error in this Verilog expression:

wire result = a & b | c;

Assuming a, b, and c are 1-bit wires.

medium

A. No error; expression is valid and precedence is correct

B. Expression needs parentheses to clarify order

C. Logical operators should be used instead of bitwise

D. Bitwise AND (&) has lower precedence than bitwise OR (|)

Solution

1. Step 1: Check operator precedence

   Bitwise AND (&) has higher precedence than bitwise OR (|), so a & b is evaluated first.

2. Step 2: Validate expression correctness

   Since a & b is evaluated before OR with c, the expression is valid and no parentheses are required.

3. Final Answer:

   No error; expression is valid and precedence is correct -> Option A

4. Quick Check:

   Bitwise AND > Bitwise OR, so expression is correct [OK]

Hint: Bitwise AND has higher precedence than OR, no parentheses needed [OK]

Common Mistakes:

• Assuming bitwise OR has higher precedence than AND
• Adding unnecessary parentheses
• Confusing bitwise and logical operators

5. Consider this Verilog expression:

wire [3:0] x = 4; wire [3:0] y = 2; wire [3:0] z = 1;
wire [3:0] out = x + y << z & 3;

What is the correct order of operations to evaluate out?

hard

A. Add x + y, then shift left by z, then bitwise AND with 3

B. Shift y left by z, bitwise AND with 3, then add x

C. Bitwise AND y with 3, shift left by z, then add x

D. Add x + y, bitwise AND with 3, then shift left by z

Solution

1. Step 1: Identify operator precedence

   Shift (<<) has higher precedence than addition (+), and addition (+) has higher precedence than bitwise AND (&).

2. Step 2: Determine evaluation order

   First, y << z is evaluated, then bitwise AND with 3, then finally add x.

3. Final Answer:

   Shift y left by z, bitwise AND with 3, then add x -> Option B

4. Quick Check:

   << > & > + so x + ((y << z) & 3) [OK]

Hint: Shift > bitwise AND > addition in Verilog precedence [OK]

Common Mistakes:

• Assuming shift happens after addition
• Confusing shift and addition precedence
• Ignoring operator precedence rules for shift