Generating clock signal in testbench in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output waveform behavior of this clock generator?

Consider this Verilog testbench snippet that generates a clock signal. What is the frequency of the clock signal produced?

reg clk = 0;
always #5 clk = ~clk;

Verilog

reg clk = 0;
always #5 clk = ~clk;

A Clock period is 10 time units, frequency is 0.1 units^-1

B Clock period is 5 time units, frequency is 0.2 units^-1

C Clock period is 5 time units, frequency is 0.1 units^-1

D Clock period is 10 time units, frequency is 0.2 units^-1

💡 Hint

The clock toggles every 5 time units, so a full cycle is twice that.

The clock toggles every 5 time units, so one full period is 10 time units. Frequency is 1/period = 1/10 = 0.1 units^-1. This matches option A.

❓ Predict Output

intermediate

What is the initial value of clk after this testbench code runs?

Given this Verilog testbench code:

reg clk;
initial begin
  clk = 1'b1;
  #10 clk = 1'b0;
end

What is the value of clk at time 0?

Verilog

reg clk;
initial begin
  clk = 1'b1;
  #10 clk = 1'b0;
end

A clk toggles immediately at time 0

B clk is 0 at time 0

C clk is undefined at time 0

D clk is 1 at time 0

💡 Hint

Initial block runs at time 0 and sets clk first.

The initial block sets clk to 1 at time 0, then after 10 time units sets clk to 0.

🔧 Debug

advanced

Why does this clock generator not toggle as expected?

Look at this Verilog code snippet intended to generate a clock signal:

reg clk = 0;
always (clk) #5 clk = ~clk;

What is the problem?

Verilog

reg clk = 0;
always (clk) #5 clk = ~clk;

A No problem, code works fine

B Syntax error: always block requires @ or no sensitivity list

C clk is not initialized

D Clock toggles too fast causing simulation crash

💡 Hint

Check the syntax of the always block sensitivity list.

The always block sensitivity list must be empty, or use @ (posedge clk) or similar. '(clk)' is invalid syntax.

🚀 Application

advanced

How to generate a 50 MHz clock from a 100 MHz input clock in testbench?

You have a 100 MHz clock signal in your testbench. Which code snippet correctly generates a 50 MHz clock by dividing the input clock by 2?

A always @(negedge clk_in) clk_out = clk_out + 1;

B always @(posedge clk_in) clk_out = clk_out + 1;

C always @(posedge clk_in) clk_out <= ~clk_out;

D always @(posedge clk_in) clk_out <= clk_out + 1;

💡 Hint

Toggle output clock on every rising edge of input clock.

Toggling clk_out on every positive edge of clk_in divides frequency by 2, producing 50 MHz from 100 MHz.

🧠 Conceptual

expert

What is the effect of using non-blocking assignment in clock generation always block?

In a testbench, you write:

reg clk = 0;
always #5 clk <= ~clk;

What is the effect of using non-blocking assignment (<=) instead of blocking (=) here?

Verilog

reg clk = 0;
always #5 clk <= ~clk;

A No difference in simulation behavior for this clock generation

B Clock will not toggle correctly, simulation hangs

C Clock toggles twice as fast

D Simulation throws a syntax error

💡 Hint

Non-blocking and blocking assignments behave similarly in simple clock toggling.

For simple clock toggling in testbench, blocking or non-blocking assignments produce the same waveform.

Practice

1. What is the main purpose of generating a clock signal in a Verilog testbench?

easy

A. To provide timing reference for sequential logic simulation

B. To initialize all variables to zero

C. To display output results on the console

D. To declare input and output ports

Solution

1. Step 1: Understand the role of clock in digital circuits

   The clock signal acts as a timing reference that controls when sequential elements update their state.

2. Step 2: Relate clock generation to testbench function

   In a testbench, generating a clock allows the simulation of sequential logic behavior over time.

3. Final Answer:

   To provide timing reference for sequential logic simulation -> Option A

4. Quick Check:

   Clock = timing reference [OK]

Hint: Clock controls timing in sequential circuits [OK]

Common Mistakes:

• Confusing clock with variable initialization
• Thinking clock displays output
• Assuming clock declares ports

2. Which of the following is the correct way to toggle a clock signal every 5 time units in a Verilog testbench?

easy

A. always #5 clk = ~clk;

B. initial #5 forever clk = ~clk;

C. initial #5 clk = ~clk;

D. always clk = ~clk #5;

Solution

1. Step 1: Identify correct syntax for clock toggling

   The always block with a delay #5 toggles the clock repeatedly every 5 time units.

2. Step 2: Check each option's correctness

   always #5 clk = ~clk; uses always #5 clk = ~clk; which is the standard way to toggle clock periodically.

3. Final Answer:

   always #5 clk = ~clk; -> Option A

4. Quick Check:

   Toggle clock with always and delay [OK]

Hint: Use always with delay to toggle clock [OK]

Common Mistakes:

• Using initial with forever incorrectly
• Placing delay after assignment
• Missing forever or always block

3. Given the following Verilog testbench code snippet, what will be the value of clk at time 15?

reg clk = 0;\nalways #5 clk = ~clk;

medium

A. x (unknown)

B. 0

C. It will cause a syntax error

D. 1

Solution

1. Step 1: Analyze clock toggling timing

   Clock starts at 0, toggles every 5 time units: at 5 (1), 10 (0), 15 (1).

2. Step 2: Determine clock value at time 15

   At time 15, clock toggles to 1.

3. Final Answer:

   1 -> Option D

4. Quick Check:

   Toggle every 5 units, time 15 = 1 [OK]

Hint: Toggle flips every 5 units, count toggles [OK]

Common Mistakes:

• Forgetting initial clock value
• Miscounting toggle times
• Assuming syntax error without cause

4. Identify the error in this clock generation code snippet:

reg clk = 0;\ninitial begin\n  forever clk = #10 ~clk;\nend

medium

A. Missing semicolon after forever statement

B. Delay operator (#10) is incorrectly placed after assignment

C. Initial block cannot contain forever loop

D. Clock should be declared as wire, not reg

Solution

1. Step 1: Check delay placement in assignment

   Delay operator should precede the assignment, not be after it.

2. Step 2: Correct syntax for toggling clock with delay

   Correct form: forever #10 clk = ~clk; places delay before assignment.

3. Final Answer:

   Delay operator (#10) is incorrectly placed after assignment -> Option B

4. Quick Check:

   Delay before assignment, not after [OK]

Hint: Put #delay before assignment in forever loop [OK]

Common Mistakes:

• Placing #delay after assignment
• Confusing reg and wire for clock
• Thinking forever loops not allowed in initial

5. You want to generate a 50 MHz clock signal in a Verilog testbench. What is the correct delay value to toggle the clock if the time unit is 1ns?

hard

A. #1 (1 ns delay)

B. #20 (20 ns delay)

C. #10 (10 ns delay)

D. #5 (5 ns delay)

Solution

1. Step 1: Calculate clock period from frequency

   Frequency 50 MHz means period = 1 / 50e6 = 20 ns.

2. Step 2: Determine toggle delay for half period

   Clock toggles every half period, so delay = 20 ns / 2 = 10 ns.

3. Final Answer:

   #10 (10 ns delay) -> Option C

4. Quick Check:

   Half period delay = 10 ns for 50 MHz [OK]

Hint: Toggle delay = half clock period [OK]

Common Mistakes:

• Using full period as delay
• Confusing frequency and period
• Ignoring time unit scale