NVIC (Nested Vectored Interrupt Controller) in ARM Architecture - Step-by-Step Execution

Concept Flow - NVIC (Nested Vectored Interrupt Controller)

Interrupt Occurs

↓

Is Interrupt Enabled?

No→Ignore Interrupt

Yes↓

NVIC Checks Priority

↓

Save Current Context

↓

Jump to Interrupt Handler

↓

Execute Handler

↓

Restore Context

↓

Return to Main Program

When an interrupt occurs, NVIC checks if it is enabled and its priority, then saves the current state, runs the interrupt handler, and finally restores the state to continue the main program.

Execution Sample

ARM Architecture

Interrupt occurs
NVIC checks priority and enable
If enabled, save context
Jump to handler
Execute handler
Restore context and return

This sequence shows how NVIC handles an interrupt from detection to returning to the main program.

Analysis Table

Step	Action	Condition/Check	Result/Output
1	Interrupt signal detected	Interrupt occurs	NVIC starts processing
2	Check if interrupt is enabled	Interrupt enabled?	Yes -> proceed; No -> ignore
3	Check interrupt priority	Priority compared to current	If higher priority, proceed
4	Save current CPU context	Context saved	Registers and state saved
5	Jump to interrupt handler	Handler address fetched	Program counter set to handler
6	Execute interrupt handler	Handler code runs	Interrupt serviced
7	Restore CPU context	Context restored	Registers and state restored
8	Return to main program	Return from interrupt	Program resumes normal execution
9	End	No more interrupts	NVIC waits for next interrupt

💡 Interrupt handled and CPU context restored, returning to main program execution

State Tracker

Variable	Start	After Step 4	After Step 7	Final
Interrupt Enabled Flag	Depends on config	Checked	Checked	No change
Interrupt Priority	Set by user	Checked	Checked	No change
CPU Context (Registers)	Main program state	Saved	Restored	Main program state restored
Program Counter (PC)	Main program address	Set to handler	Set back to main	Main program address

Key Insights - 3 Insights

Why does NVIC save the CPU context before running the interrupt handler?

NVIC saves the CPU context (Step 4 in execution_table) so that after the interrupt handler finishes, the main program can resume exactly where it left off without losing any data.

What happens if the interrupt is not enabled when it occurs?

If the interrupt is not enabled (Step 2 in execution_table), NVIC ignores it and does not run the handler, so the main program continues uninterrupted.

How does NVIC decide which interrupt to handle first if multiple occur?

NVIC compares the priority of interrupts (Step 3 in execution_table) and handles the one with the highest priority first.

Visual Quiz - 3 Questions

Look at the execution_table, at which step does NVIC save the CPU context?

A Step 4

B Step 6

C Step 2

D Step 8

💡 Hint

Check the 'Action' column for 'Save current CPU context' in execution_table.

According to variable_tracker, what happens to the Program Counter after Step 5?

A It is reset to zero

B It remains at the main program address

C It is set to the interrupt handler address

D It is saved and not changed

💡 Hint

Look at the 'Program Counter (PC)' row in variable_tracker after Step 4 and Step 7.

If an interrupt is disabled, what does NVIC do according to the execution_table?

A Runs the interrupt handler anyway

B Ignores the interrupt

C Saves context but skips handler

D Restarts the CPU

💡 Hint

See Step 2 in execution_table under 'Condition/Check' and 'Result/Output'.

Concept Snapshot

NVIC handles interrupts by checking if they are enabled and their priority.
If enabled and highest priority, it saves CPU context, runs the interrupt handler, then restores context.
This allows the main program to pause and resume seamlessly.
NVIC supports nested interrupts by priority.
It is essential for responsive embedded systems.

Full Transcript

The Nested Vectored Interrupt Controller (NVIC) manages interrupts in ARM processors. When an interrupt occurs, NVIC first checks if the interrupt is enabled and compares its priority with others. If the interrupt is enabled and has sufficient priority, NVIC saves the current CPU context, including registers and program counter. Then it jumps to the interrupt handler to execute the interrupt service routine. After the handler finishes, NVIC restores the saved CPU context so the main program can continue exactly where it left off. If the interrupt is not enabled, NVIC ignores it. NVIC allows multiple interrupts to be prioritized and nested, ensuring critical tasks are handled promptly without losing program state.

Practice

1. What is the main purpose of the NVIC in ARM microcontrollers?

easy

A. To increase the clock speed of the processor

B. To manage and prioritize multiple interrupts efficiently

C. To store program instructions

D. To handle memory allocation

Solution

1. Step 1: Understand NVIC's role

   NVIC stands for Nested Vectored Interrupt Controller, which manages interrupts.

2. Step 2: Identify its main function

   It enables, disables, and prioritizes interrupts so the processor can respond quickly to important events.

3. Final Answer:

   To manage and prioritize multiple interrupts efficiently -> Option B

4. Quick Check:

   NVIC controls interrupts = B [OK]

Hint: NVIC is about interrupt control, not speed or memory [OK]

Common Mistakes:

• Confusing NVIC with clock or memory functions
• Thinking NVIC stores program code
• Assuming NVIC increases processor speed

2. Which of the following is the correct way to enable an interrupt using NVIC in ARM Cortex-M?

easy

A. NVIC_SetPriority(IRQn, priority);

B. NVIC_DisableIRQ(IRQn);

C. NVIC_EnableIRQ(IRQn);

D. NVIC_ClearPendingIRQ(IRQn);

Solution

1. Step 1: Identify function purpose

   NVIC_EnableIRQ is used to enable a specific interrupt request (IRQ).

2. Step 2: Compare other options

   NVIC_DisableIRQ disables interrupts, NVIC_SetPriority sets priority, NVIC_ClearPendingIRQ clears pending interrupts.

3. Final Answer:

   NVIC_EnableIRQ(IRQn); -> Option C

4. Quick Check:

   Enable interrupt function = NVIC_EnableIRQ [OK]

Hint: Enable interrupts with NVIC_EnableIRQ function [OK]

Common Mistakes:

• Confusing enable with disable functions
• Mixing priority setting with enabling
• Using clear pending instead of enable

3. Consider the following code snippet for ARM Cortex-M NVIC:

NVIC_SetPriority(TIM2_IRQn, 2);
NVIC_EnableIRQ(TIM2_IRQn);
NVIC_SetPriority(USART1_IRQn, 1);
NVIC_EnableIRQ(USART1_IRQn);

Which interrupt has higher priority?

medium

A. USART1_IRQn has higher priority

B. TIM2_IRQn has higher priority

C. Both have equal priority

D. Priority cannot be determined

Solution

1. Step 1: Understand priority values

   Lower numeric priority value means higher priority in NVIC.

2. Step 2: Compare priorities set

   TIM2_IRQn is set to 2, USART1_IRQn is set to 1, so USART1_IRQn has higher priority.

3. Final Answer:

   USART1_IRQn has higher priority -> Option A

4. Quick Check:

   Lower number = higher priority = USART1_IRQn [OK]

Hint: Lower priority number means higher priority [OK]

Common Mistakes:

• Assuming higher number means higher priority
• Ignoring priority values and focusing on enable order
• Confusing IRQ names

4. A developer wrote this code to disable an interrupt but it does not work as expected:

NVIC_EnableIRQ(EXTI0_IRQn);
NVIC_DisableIRQ(EXTI1_IRQn);

What is the likely mistake?

medium

A. The priority must be set before disabling

B. NVIC_DisableIRQ cannot disable interrupts

C. Interrupts must be disabled before enabling

D. They enabled EXTI0_IRQn but disabled EXTI1_IRQn instead

Solution

1. Step 1: Analyze the code

   The code enables EXTI0_IRQn but disables EXTI1_IRQn, which are different interrupts.

2. Step 2: Identify the mistake

   If the goal was to disable EXTI0_IRQn, disabling EXTI1_IRQn is incorrect.

3. Final Answer:

   They enabled EXTI0_IRQn but disabled EXTI1_IRQn instead -> Option D

4. Quick Check:

   Mismatch in IRQ numbers = mistake [OK]

Hint: Check IRQ names carefully when enabling/disabling [OK]

Common Mistakes:

• Disabling wrong interrupt number
• Believing disable function doesn't work
• Thinking priority affects disabling

5. You want to ensure that a critical sensor interrupt always preempts a less important communication interrupt. How should you configure NVIC priorities for SENSOR_IRQn and COMM_IRQn?

hard

A. Set SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1)

B. Set SENSOR_IRQn priority higher than COMM_IRQn (e.g., SENSOR=2, COMM=1)

C. Disable COMM_IRQn and enable SENSOR_IRQn only

D. Set both priorities equal and enable both

Solution

1. Step 1: Recall NVIC priority rules

   Lower numeric priority means higher priority and can preempt others.

2. Step 2: Apply to SENSOR and COMM interrupts

   To let SENSOR_IRQn preempt COMM_IRQn, SENSOR_IRQn must have a lower priority number.

3. Final Answer:

   Set SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1) -> Option A

4. Quick Check:

   Lower number = higher priority = SENSOR_IRQn preempts [OK]

Hint: Lower priority number means higher interrupt priority [OK]

Common Mistakes:

• Assigning higher number for higher priority
• Disabling interrupts instead of prioritizing
• Setting equal priorities expecting preemption