NVIC (Nested Vectored Interrupt Controller) in ARM Architecture - Time & Space Complexity

Time Complexity: NVIC (Nested Vectored Interrupt Controller)

O(n)

Understanding Time Complexity

When working with the NVIC, it is important to understand how interrupt handling time grows as the number of interrupts increases.

We want to know how the time to process interrupts changes when more interrupts are enabled or pending.

Scenario Under Consideration

Analyze the time complexity of checking and servicing interrupts in NVIC.

// Simplified NVIC interrupt handling loop
while (1) {
  for (int i = 0; i < NUM_INTERRUPTS; i++) {
    if (NVIC->ISPR[i / 32] & (1 << (i % 32))) {
      NVIC->ICPR[i / 32] = (1 << (i % 32)); // Clear pending
      handle_interrupt(i); // Service interrupt
    }
  }
}
    

This code checks each possible interrupt line to see if it is pending, clears it, and then handles it.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: Looping through all interrupt lines to check pending status.
• How many times: Once per main loop iteration, checking each interrupt line.

How Execution Grows With Input

As the number of interrupts (n) increases, the time to check all lines grows proportionally.

Input Size (n)	Approx. Operations
10	10 checks
100	100 checks
1000	1000 checks

Pattern observation: The number of checks grows linearly with the number of interrupts.

Final Time Complexity

Time Complexity: O(n)

This means the time to check and handle interrupts grows directly in proportion to the number of interrupt lines.

Common Mistake

[X] Wrong: "Checking interrupts happens instantly regardless of how many interrupts exist."

[OK] Correct: Each interrupt line must be checked, so more interrupts mean more work and longer checking time.

Interview Connect

Understanding how interrupt checking scales helps you reason about system responsiveness and efficiency in embedded systems.

Self-Check

"What if the NVIC used a hardware priority encoder to find the highest priority pending interrupt instead of checking all lines? How would the time complexity change?"

Practice

1. What is the main purpose of the NVIC in ARM microcontrollers?

easy

A. To increase the clock speed of the processor

B. To manage and prioritize multiple interrupts efficiently

C. To store program instructions

D. To handle memory allocation

Solution

1. Step 1: Understand NVIC's role

   NVIC stands for Nested Vectored Interrupt Controller, which manages interrupts.

2. Step 2: Identify its main function

   It enables, disables, and prioritizes interrupts so the processor can respond quickly to important events.

3. Final Answer:

   To manage and prioritize multiple interrupts efficiently -> Option B

4. Quick Check:

   NVIC controls interrupts = B [OK]

Hint: NVIC is about interrupt control, not speed or memory [OK]

Common Mistakes:

• Confusing NVIC with clock or memory functions
• Thinking NVIC stores program code
• Assuming NVIC increases processor speed

2. Which of the following is the correct way to enable an interrupt using NVIC in ARM Cortex-M?

easy

A. NVIC_SetPriority(IRQn, priority);

B. NVIC_DisableIRQ(IRQn);

C. NVIC_EnableIRQ(IRQn);

D. NVIC_ClearPendingIRQ(IRQn);

Solution

1. Step 1: Identify function purpose

   NVIC_EnableIRQ is used to enable a specific interrupt request (IRQ).

2. Step 2: Compare other options

   NVIC_DisableIRQ disables interrupts, NVIC_SetPriority sets priority, NVIC_ClearPendingIRQ clears pending interrupts.

3. Final Answer:

   NVIC_EnableIRQ(IRQn); -> Option C

4. Quick Check:

   Enable interrupt function = NVIC_EnableIRQ [OK]

Hint: Enable interrupts with NVIC_EnableIRQ function [OK]

Common Mistakes:

• Confusing enable with disable functions
• Mixing priority setting with enabling
• Using clear pending instead of enable

3. Consider the following code snippet for ARM Cortex-M NVIC:

NVIC_SetPriority(TIM2_IRQn, 2);
NVIC_EnableIRQ(TIM2_IRQn);
NVIC_SetPriority(USART1_IRQn, 1);
NVIC_EnableIRQ(USART1_IRQn);

Which interrupt has higher priority?

medium

A. USART1_IRQn has higher priority

B. TIM2_IRQn has higher priority

C. Both have equal priority

D. Priority cannot be determined

Solution

1. Step 1: Understand priority values

   Lower numeric priority value means higher priority in NVIC.

2. Step 2: Compare priorities set

   TIM2_IRQn is set to 2, USART1_IRQn is set to 1, so USART1_IRQn has higher priority.

3. Final Answer:

   USART1_IRQn has higher priority -> Option A

4. Quick Check:

   Lower number = higher priority = USART1_IRQn [OK]

Hint: Lower priority number means higher priority [OK]

Common Mistakes:

• Assuming higher number means higher priority
• Ignoring priority values and focusing on enable order
• Confusing IRQ names

4. A developer wrote this code to disable an interrupt but it does not work as expected:

NVIC_EnableIRQ(EXTI0_IRQn);
NVIC_DisableIRQ(EXTI1_IRQn);

What is the likely mistake?

medium

A. The priority must be set before disabling

B. NVIC_DisableIRQ cannot disable interrupts

C. Interrupts must be disabled before enabling

D. They enabled EXTI0_IRQn but disabled EXTI1_IRQn instead

Solution

1. Step 1: Analyze the code

   The code enables EXTI0_IRQn but disables EXTI1_IRQn, which are different interrupts.

2. Step 2: Identify the mistake

   If the goal was to disable EXTI0_IRQn, disabling EXTI1_IRQn is incorrect.

3. Final Answer:

   They enabled EXTI0_IRQn but disabled EXTI1_IRQn instead -> Option D

4. Quick Check:

   Mismatch in IRQ numbers = mistake [OK]

Hint: Check IRQ names carefully when enabling/disabling [OK]

Common Mistakes:

• Disabling wrong interrupt number
• Believing disable function doesn't work
• Thinking priority affects disabling

5. You want to ensure that a critical sensor interrupt always preempts a less important communication interrupt. How should you configure NVIC priorities for SENSOR_IRQn and COMM_IRQn?

hard

A. Set SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1)

B. Set SENSOR_IRQn priority higher than COMM_IRQn (e.g., SENSOR=2, COMM=1)

C. Disable COMM_IRQn and enable SENSOR_IRQn only

D. Set both priorities equal and enable both

Solution

1. Step 1: Recall NVIC priority rules

   Lower numeric priority means higher priority and can preempt others.

2. Step 2: Apply to SENSOR and COMM interrupts

   To let SENSOR_IRQn preempt COMM_IRQn, SENSOR_IRQn must have a lower priority number.

3. Final Answer:

   Set SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1) -> Option A

4. Quick Check:

   Lower number = higher priority = SENSOR_IRQn preempts [OK]

Hint: Lower priority number means higher interrupt priority [OK]

Common Mistakes:

• Assigning higher number for higher priority
• Disabling interrupts instead of prioritizing
• Setting equal priorities expecting preemption