Exception priority levels in ARM Architecture

Introduction

Exception priority levels help the processor decide which interrupt or error to handle first when multiple happen at the same time.

When multiple hardware interrupts occur simultaneously and the processor must choose which one to handle first.

When designing embedded systems that need to respond quickly to critical events.

When programming ARM processors to manage different types of exceptions like faults, interrupts, or system calls.

When debugging why certain interrupts are delayed or not serviced promptly.

When configuring the Nested Vectored Interrupt Controller (NVIC) in ARM Cortex processors.

Core Concept

ARM Architecture

Exception priority levels are assigned as numeric values, where a lower number means higher priority.
For example:
Priority 0 = highest priority
Priority 255 = lowest priority

Priority levels are usually set in the interrupt controller registers.

Lower numeric values mean higher priority, so 0 is the highest priority.

Key Points

This sets interrupt number 5 to priority level 2, which is high priority but not the highest.

ARM Architecture

Set priority of interrupt 5 to 2
NVIC_SetPriority(5, 2);

This sets interrupt number 10 to a lower priority, so it will be handled after higher priority interrupts.

ARM Architecture

Set priority of interrupt 10 to 10
NVIC_SetPriority(10, 10);

Detailed Explanation

This example sets two interrupts with different priorities. Interrupt 3 has the highest priority (0), so it will be handled before interrupt 7, which has priority 5.

ARM Architecture

#include "stm32f4xx.h"

int main() {
    // Set priority for interrupt 3 to highest (0)
    NVIC_SetPriority(3, 0);
    // Set priority for interrupt 7 to lower (5)
    NVIC_SetPriority(7, 5);

    // Enable interrupts
    NVIC_EnableIRQ(3);
    NVIC_EnableIRQ(7);

    while(1) {
        // Main loop
    }
    return 0;
}

Important Notes

Exception priority levels allow critical tasks to interrupt less important ones.

Some ARM processors support grouping priorities to manage preemption and subpriority.

Always check your processor's documentation for the number of priority bits supported.

Summary

Exception priority levels determine the order in which interrupts are handled.

Lower numeric priority means higher importance.

Setting priorities helps manage multiple simultaneous exceptions efficiently.