NVIC (Nested Vectored Interrupt Controller) in ARM Architecture - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the primary role of the NVIC in ARM Cortex-M processors?

The NVIC manages and prioritizes interrupts, allowing the processor to respond quickly and efficiently to multiple interrupt sources.

beginner

What does 'vectored' mean in the context of NVIC?

'Vectored' means that each interrupt has a specific address (vector) where the processor jumps to handle that interrupt, enabling fast and direct interrupt handling.

intermediate

How does NVIC prioritize interrupts?

NVIC assigns priority levels to interrupts, so higher priority interrupts can preempt lower priority ones, ensuring critical tasks are handled first.

intermediate

What is 'nested' in Nested Vectored Interrupt Controller?

'Nested' means that while handling one interrupt, the NVIC can allow a higher priority interrupt to interrupt the current one, enabling multiple levels of interrupt handling.

advanced

How does NVIC improve system responsiveness compared to traditional interrupt controllers?

NVIC provides fast interrupt vectoring, dynamic priority management, and nesting, which reduces latency and improves real-time responsiveness.

What feature allows NVIC to handle multiple interrupts efficiently?

A Single interrupt queue

B Nested interrupt handling

C Polling interrupts

D Fixed priority without preemption

NVIC supports nested interrupt handling, allowing higher priority interrupts to preempt lower priority ones for efficient processing.

In NVIC, what does the interrupt vector point to?

A The interrupt enable register

B The interrupt priority level

C The processor status register

D The address of the interrupt handler function

The interrupt vector is the address where the processor jumps to execute the interrupt handler.

Which of the following is NOT a benefit of NVIC?

A Eliminates the need for interrupt handlers

B Dynamic priority management

C Supports nested interrupts

D Fast interrupt response

NVIC requires interrupt handlers; it does not eliminate the need for them.

What happens when a higher priority interrupt occurs during a lower priority interrupt in NVIC?

A The lower priority interrupt continues until completion

B Both interrupts are ignored

C The higher priority interrupt preempts the lower priority one

D The system resets

NVIC allows higher priority interrupts to preempt lower priority ones, enabling nested interrupt handling.

Which ARM processor family commonly uses NVIC?

A ARM Cortex-M

B ARM Cortex-A

C ARM7

D ARM9

NVIC is a feature of ARM Cortex-M processors designed for embedded real-time applications.

Explain how NVIC manages multiple interrupts and why this is important for real-time systems.

Think about how the system decides which interrupt to handle first and how it can switch between them.

Describe the meaning of 'vectored' and 'nested' in NVIC and how they work together.

Consider how the processor knows where to go for each interrupt and how it handles multiple interrupts at once.

Practice

1. What is the main purpose of the NVIC in ARM microcontrollers?

easy

A. To increase the clock speed of the processor

B. To manage and prioritize multiple interrupts efficiently

C. To store program instructions

D. To handle memory allocation

Solution

1. Step 1: Understand NVIC's role

   NVIC stands for Nested Vectored Interrupt Controller, which manages interrupts.

2. Step 2: Identify its main function

   It enables, disables, and prioritizes interrupts so the processor can respond quickly to important events.

3. Final Answer:

   To manage and prioritize multiple interrupts efficiently -> Option B

4. Quick Check:

   NVIC controls interrupts = B [OK]

Hint: NVIC is about interrupt control, not speed or memory [OK]

Common Mistakes:

• Confusing NVIC with clock or memory functions
• Thinking NVIC stores program code
• Assuming NVIC increases processor speed

2. Which of the following is the correct way to enable an interrupt using NVIC in ARM Cortex-M?

easy

A. NVIC_SetPriority(IRQn, priority);

B. NVIC_DisableIRQ(IRQn);

C. NVIC_EnableIRQ(IRQn);

D. NVIC_ClearPendingIRQ(IRQn);

Solution

1. Step 1: Identify function purpose

   NVIC_EnableIRQ is used to enable a specific interrupt request (IRQ).

2. Step 2: Compare other options

   NVIC_DisableIRQ disables interrupts, NVIC_SetPriority sets priority, NVIC_ClearPendingIRQ clears pending interrupts.

3. Final Answer:

   NVIC_EnableIRQ(IRQn); -> Option C

4. Quick Check:

   Enable interrupt function = NVIC_EnableIRQ [OK]

Hint: Enable interrupts with NVIC_EnableIRQ function [OK]

Common Mistakes:

• Confusing enable with disable functions
• Mixing priority setting with enabling
• Using clear pending instead of enable

3. Consider the following code snippet for ARM Cortex-M NVIC:

NVIC_SetPriority(TIM2_IRQn, 2);
NVIC_EnableIRQ(TIM2_IRQn);
NVIC_SetPriority(USART1_IRQn, 1);
NVIC_EnableIRQ(USART1_IRQn);

Which interrupt has higher priority?

medium

A. USART1_IRQn has higher priority

B. TIM2_IRQn has higher priority

C. Both have equal priority

D. Priority cannot be determined

Solution

1. Step 1: Understand priority values

   Lower numeric priority value means higher priority in NVIC.

2. Step 2: Compare priorities set

   TIM2_IRQn is set to 2, USART1_IRQn is set to 1, so USART1_IRQn has higher priority.

3. Final Answer:

   USART1_IRQn has higher priority -> Option A

4. Quick Check:

   Lower number = higher priority = USART1_IRQn [OK]

Hint: Lower priority number means higher priority [OK]

Common Mistakes:

• Assuming higher number means higher priority
• Ignoring priority values and focusing on enable order
• Confusing IRQ names

4. A developer wrote this code to disable an interrupt but it does not work as expected:

NVIC_EnableIRQ(EXTI0_IRQn);
NVIC_DisableIRQ(EXTI1_IRQn);

What is the likely mistake?

medium

A. The priority must be set before disabling

B. NVIC_DisableIRQ cannot disable interrupts

C. Interrupts must be disabled before enabling

D. They enabled EXTI0_IRQn but disabled EXTI1_IRQn instead

Solution

1. Step 1: Analyze the code

   The code enables EXTI0_IRQn but disables EXTI1_IRQn, which are different interrupts.

2. Step 2: Identify the mistake

   If the goal was to disable EXTI0_IRQn, disabling EXTI1_IRQn is incorrect.

3. Final Answer:

   They enabled EXTI0_IRQn but disabled EXTI1_IRQn instead -> Option D

4. Quick Check:

   Mismatch in IRQ numbers = mistake [OK]

Hint: Check IRQ names carefully when enabling/disabling [OK]

Common Mistakes:

• Disabling wrong interrupt number
• Believing disable function doesn't work
• Thinking priority affects disabling

5. You want to ensure that a critical sensor interrupt always preempts a less important communication interrupt. How should you configure NVIC priorities for SENSOR_IRQn and COMM_IRQn?

hard

A. Set SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1)

B. Set SENSOR_IRQn priority higher than COMM_IRQn (e.g., SENSOR=2, COMM=1)

C. Disable COMM_IRQn and enable SENSOR_IRQn only

D. Set both priorities equal and enable both

Solution

1. Step 1: Recall NVIC priority rules

   Lower numeric priority means higher priority and can preempt others.

2. Step 2: Apply to SENSOR and COMM interrupts

   To let SENSOR_IRQn preempt COMM_IRQn, SENSOR_IRQn must have a lower priority number.

3. Final Answer:

   Set SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1) -> Option A

4. Quick Check:

   Lower number = higher priority = SENSOR_IRQn preempts [OK]

Hint: Lower priority number means higher interrupt priority [OK]

Common Mistakes:

• Assigning higher number for higher priority
• Disabling interrupts instead of prioritizing
• Setting equal priorities expecting preemption