NVIC (Nested Vectored Interrupt Controller) in ARM Architecture - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to enable an interrupt in the NVIC.

ARM Architecture

NVIC->ISER[0] = 1 << [1];

Drag options to blanks, or click blank then click option'

A3

B5

C10

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Using the interrupt number directly without shifting.

Using an incorrect interrupt number.

The NVIC interrupt set-enable register (ISER) uses bit positions to enable interrupts. Shifting 1 by the interrupt number enables that interrupt. Here, 3 is the correct interrupt number to enable.

2fill in blank

medium

Complete the code to set the priority of an interrupt in the NVIC.

ARM Architecture

NVIC->IP[[1]] = 0x20;

Drag options to blanks, or click blank then click option'

A5

B10

C0

D2

Attempts:

3 left

💡 Hint

Common Mistakes

Using a wrong index that does not match the interrupt number.

Confusing priority value with interrupt number.

The NVIC interrupt priority register (IP) array uses the interrupt number as the index. Setting IP[2] assigns priority to interrupt number 2.

3fill in blank

hard

Fix the error in the code to disable an interrupt in the NVIC.

ARM Architecture

NVIC->[1][0] = 1 << 4;

Drag options to blanks, or click blank then click option'

AICER

BICPR

CISPR

DISER

Attempts:

3 left

💡 Hint

Common Mistakes

Using ISER instead of ICER to disable interrupts.

Using pending registers instead of enable/disable registers.

To disable an interrupt, the NVIC interrupt clear-enable register (ICER) must be used, not ISER which enables interrupts.

4fill in blank

hard

Fill both blanks to check if interrupt 7 is pending and clear it in the NVIC.

ARM Architecture

if (NVIC->[1][0] & (1 << 7)) {
    NVIC->[2][0] = 1 << 7;
}

Drag options to blanks, or click blank then click option'

AISPR

BICPR

CISER

DICER

Attempts:

3 left

💡 Hint

Common Mistakes

Using enable/disable registers instead of pending registers.

Confusing set-pending with clear-pending registers.

ISPR is the interrupt set-pending register used to check if an interrupt is pending. ICPR is the interrupt clear-pending register used to clear the pending status.

5fill in blank

hard

Fill all three blanks to create a dictionary comprehension that maps interrupt numbers to their priority if priority is less than 128.

ARM Architecture

{ [1]: NVIC.IP[[2]] for [3] in range(32) if NVIC.IP[[2]] < 128 }

Drag options to blanks, or click blank then click option'

Ai

Dj

Attempts:

3 left

💡 Hint

Common Mistakes

Using different variable names inconsistently.

Using a variable not defined in the comprehension.

Using 'i' as the loop variable and key/index variable is standard. The comprehension maps interrupt number i to its priority if priority is less than 128.

Practice

1. What is the main purpose of the NVIC in ARM microcontrollers?

easy

A. To increase the clock speed of the processor

B. To manage and prioritize multiple interrupts efficiently

C. To store program instructions

D. To handle memory allocation

Solution

1. Step 1: Understand NVIC's role

   NVIC stands for Nested Vectored Interrupt Controller, which manages interrupts.

2. Step 2: Identify its main function

   It enables, disables, and prioritizes interrupts so the processor can respond quickly to important events.

3. Final Answer:

   To manage and prioritize multiple interrupts efficiently -> Option B

4. Quick Check:

   NVIC controls interrupts = B [OK]

Hint: NVIC is about interrupt control, not speed or memory [OK]

Common Mistakes:

• Confusing NVIC with clock or memory functions
• Thinking NVIC stores program code
• Assuming NVIC increases processor speed

2. Which of the following is the correct way to enable an interrupt using NVIC in ARM Cortex-M?

easy

A. NVIC_SetPriority(IRQn, priority);

B. NVIC_DisableIRQ(IRQn);

C. NVIC_EnableIRQ(IRQn);

D. NVIC_ClearPendingIRQ(IRQn);

Solution

1. Step 1: Identify function purpose

   NVIC_EnableIRQ is used to enable a specific interrupt request (IRQ).

2. Step 2: Compare other options

   NVIC_DisableIRQ disables interrupts, NVIC_SetPriority sets priority, NVIC_ClearPendingIRQ clears pending interrupts.

3. Final Answer:

   NVIC_EnableIRQ(IRQn); -> Option C

4. Quick Check:

   Enable interrupt function = NVIC_EnableIRQ [OK]

Hint: Enable interrupts with NVIC_EnableIRQ function [OK]

Common Mistakes:

• Confusing enable with disable functions
• Mixing priority setting with enabling
• Using clear pending instead of enable

3. Consider the following code snippet for ARM Cortex-M NVIC:

NVIC_SetPriority(TIM2_IRQn, 2);
NVIC_EnableIRQ(TIM2_IRQn);
NVIC_SetPriority(USART1_IRQn, 1);
NVIC_EnableIRQ(USART1_IRQn);

Which interrupt has higher priority?

medium

A. USART1_IRQn has higher priority

B. TIM2_IRQn has higher priority

C. Both have equal priority

D. Priority cannot be determined

Solution

1. Step 1: Understand priority values

   Lower numeric priority value means higher priority in NVIC.

2. Step 2: Compare priorities set

   TIM2_IRQn is set to 2, USART1_IRQn is set to 1, so USART1_IRQn has higher priority.

3. Final Answer:

   USART1_IRQn has higher priority -> Option A

4. Quick Check:

   Lower number = higher priority = USART1_IRQn [OK]

Hint: Lower priority number means higher priority [OK]

Common Mistakes:

• Assuming higher number means higher priority
• Ignoring priority values and focusing on enable order
• Confusing IRQ names

4. A developer wrote this code to disable an interrupt but it does not work as expected:

NVIC_EnableIRQ(EXTI0_IRQn);
NVIC_DisableIRQ(EXTI1_IRQn);

What is the likely mistake?

medium

A. The priority must be set before disabling

B. NVIC_DisableIRQ cannot disable interrupts

C. Interrupts must be disabled before enabling

D. They enabled EXTI0_IRQn but disabled EXTI1_IRQn instead

Solution

1. Step 1: Analyze the code

   The code enables EXTI0_IRQn but disables EXTI1_IRQn, which are different interrupts.

2. Step 2: Identify the mistake

   If the goal was to disable EXTI0_IRQn, disabling EXTI1_IRQn is incorrect.

3. Final Answer:

   They enabled EXTI0_IRQn but disabled EXTI1_IRQn instead -> Option D

4. Quick Check:

   Mismatch in IRQ numbers = mistake [OK]

Hint: Check IRQ names carefully when enabling/disabling [OK]

Common Mistakes:

• Disabling wrong interrupt number
• Believing disable function doesn't work
• Thinking priority affects disabling

5. You want to ensure that a critical sensor interrupt always preempts a less important communication interrupt. How should you configure NVIC priorities for SENSOR_IRQn and COMM_IRQn?

hard

A. Set SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1)

B. Set SENSOR_IRQn priority higher than COMM_IRQn (e.g., SENSOR=2, COMM=1)

C. Disable COMM_IRQn and enable SENSOR_IRQn only

D. Set both priorities equal and enable both

Solution

1. Step 1: Recall NVIC priority rules

   Lower numeric priority means higher priority and can preempt others.

2. Step 2: Apply to SENSOR and COMM interrupts

   To let SENSOR_IRQn preempt COMM_IRQn, SENSOR_IRQn must have a lower priority number.

3. Final Answer:

   Set SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1) -> Option A

4. Quick Check:

   Lower number = higher priority = SENSOR_IRQn preempts [OK]

Hint: Lower priority number means higher interrupt priority [OK]

Common Mistakes:

• Assigning higher number for higher priority
• Disabling interrupts instead of prioritizing
• Setting equal priorities expecting preemption