Complete the code to enable an interrupt in the NVIC.
NVIC->ISER[0] = 1 << [1];
The NVIC interrupt set-enable register (ISER) uses bit positions to enable interrupts. Shifting 1 by the interrupt number enables that interrupt. Here, 3 is the correct interrupt number to enable.
Complete the code to set the priority of an interrupt in the NVIC.
NVIC->IP[[1]] = 0x20;
The NVIC interrupt priority register (IP) array uses the interrupt number as the index. Setting IP[2] assigns priority to interrupt number 2.
Fix the error in the code to disable an interrupt in the NVIC.
NVIC->[1][0] = 1 << 4;
To disable an interrupt, the NVIC interrupt clear-enable register (ICER) must be used, not ISER which enables interrupts.
Fill both blanks to check if interrupt 7 is pending and clear it in the NVIC.
if (NVIC->[1][0] & (1 << 7)) { NVIC->[2][0] = 1 << 7; }
ISPR is the interrupt set-pending register used to check if an interrupt is pending. ICPR is the interrupt clear-pending register used to clear the pending status.
Fill all three blanks to create a dictionary comprehension that maps interrupt numbers to their priority if priority is less than 128.
{ [1]: NVIC.IP[[2]] for [3] in range(32) if NVIC.IP[[2]] < 128 }Using 'i' as the loop variable and key/index variable is standard. The comprehension maps interrupt number i to its priority if priority is less than 128.