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ARM Architectureknowledge~10 mins

NVIC (Nested Vectored Interrupt Controller) in ARM Architecture - Interactive Code Practice

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Practice - 5 Tasks
Answer the questions below
1fill in blank
easy

Complete the code to enable an interrupt in the NVIC.

ARM Architecture
NVIC->ISER[0] = 1 << [1];
Drag options to blanks, or click blank then click option'
A3
B5
C10
D0
Attempts:
3 left
💡 Hint
Common Mistakes
Using the interrupt number directly without shifting.
Using an incorrect interrupt number.
2fill in blank
medium

Complete the code to set the priority of an interrupt in the NVIC.

ARM Architecture
NVIC->IP[[1]] = 0x20;
Drag options to blanks, or click blank then click option'
A5
B10
C0
D2
Attempts:
3 left
💡 Hint
Common Mistakes
Using a wrong index that does not match the interrupt number.
Confusing priority value with interrupt number.
3fill in blank
hard

Fix the error in the code to disable an interrupt in the NVIC.

ARM Architecture
NVIC->[1][0] = 1 << 4;
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AICER
BICPR
CISPR
DISER
Attempts:
3 left
💡 Hint
Common Mistakes
Using ISER instead of ICER to disable interrupts.
Using pending registers instead of enable/disable registers.
4fill in blank
hard

Fill both blanks to check if interrupt 7 is pending and clear it in the NVIC.

ARM Architecture
if (NVIC->[1][0] & (1 << 7)) {
    NVIC->[2][0] = 1 << 7;
}
Drag options to blanks, or click blank then click option'
AISPR
BICPR
CISER
DICER
Attempts:
3 left
💡 Hint
Common Mistakes
Using enable/disable registers instead of pending registers.
Confusing set-pending with clear-pending registers.
5fill in blank
hard

Fill all three blanks to create a dictionary comprehension that maps interrupt numbers to their priority if priority is less than 128.

ARM Architecture
{ [1]: NVIC.IP[[2]] for [3] in range(32) if NVIC.IP[[2]] < 128 }
Drag options to blanks, or click blank then click option'
Ai
Dj
Attempts:
3 left
💡 Hint
Common Mistakes
Using different variable names inconsistently.
Using a variable not defined in the comprehension.