The Subroutine Call Convention (AAPCS) defines clear rules for how functions communicate in ARM systems. It helps different parts of a program work together smoothly by agreeing on how to pass data and return results.
Subroutine call convention (AAPCS) in ARM Architecture
No single code syntax; it is a set of rules about register usage and stack management during function calls.
r0-r3: Used to pass up to four integer or pointer arguments to a function. r0: Also used to return the result from a function.
r4-r11: Callee-saved registers. The called function must save and restore these if it uses them.
sp (stack pointer): Points to the current top of the stack, used for local variables and saving registers.
lr (link register): Holds the return address when a function is called.
This example shows a simple function that adds two numbers. The first two numbers are passed in registers r0 and r1. The function adds them and returns the result in r0. The link register (lr) is used to return to the caller.
; Example ARM assembly function following AAPCS ; Function: add_two_numbers ; Adds two integers passed in r0 and r1, returns result in r0 add_two_numbers: add r0, r0, r1 ; Add r1 to r0, result in r0 bx lr ; Return to caller using link register ; Caller code example mov r0, #5 ; First argument = 5 mov r1, #7 ; Second argument = 7 bl add_two_numbers ; Call function ; Result now in r0 (should be 12)
Following AAPCS ensures that functions can call each other without corrupting data.
Not following the convention can cause bugs that are hard to find, like wrong results or crashes.
Stack alignment is important; the stack pointer must be 8-byte aligned before calling a function.
AAPCS defines how ARM functions pass arguments and return values using registers.
Registers r0-r3 are for arguments and return values; r4-r11 must be preserved by the called function.
The link register (lr) holds the return address, and the stack pointer (sp) manages local data.
Practice
Solution
Step 1: Understand argument passing in AAPCS
The AAPCS specifies that the first four arguments to a subroutine are passed using registers r0, r1, r2, and r3.Step 2: Identify the correct register range
Registers r4 to r11 are used for other purposes, and lr (link register) stores the return address, not arguments.Final Answer:
r0 to r3 -> Option AQuick Check:
Arguments passed in r0-r3 [OK]
- Confusing argument registers with callee-saved registers
- Thinking lr or pc hold arguments
- Assuming stack is always used first
Solution
Step 1: Identify the purpose of the link register (lr)
In AAPCS, the link register (lr) holds the return address when a subroutine is called.Step 2: Differentiate from other registers
r0 is for return values, pc is the program counter (current instruction), and sp is the stack pointer, not for return addresses.Final Answer:
lr -> Option AQuick Check:
Return address stored in lr [OK]
- Confusing lr with pc (program counter)
- Thinking r0 holds return address
- Assuming sp stores return address
Solution
Step 1: Recall argument passing rules for more than 4 arguments
AAPCS passes the first 4 arguments in registers r0 to r3. Any additional arguments are passed on the stack.Step 2: Apply to 5 arguments
For 5 arguments, the first 4 go into r0-r3, and the 5th argument is placed on the stack.Final Answer:
First 4 in r0 to r3, 5th on the stack -> Option BQuick Check:
Extra args beyond 4 go on stack [OK]
- Assuming all args fit in registers
- Passing 5th arg in r4 incorrectly
- Ignoring stack usage for extra args
Solution
Step 1: Understand register saving responsibilities
Under AAPCS, registers r4 to r11 are callee-saved, meaning the called function must save and restore them if it uses them.Step 2: Identify the cause of unexpected change
If r4 changed unexpectedly, it means the callee did not save and restore it properly, causing corruption.Final Answer:
r4 is a callee-saved register and the callee did not save it -> Option DQuick Check:
Callee must save r4-r11 [OK]
- Thinking r4 is caller-saved
- Confusing argument registers with saved registers
- Assuming r4 holds return address
Solution
Step 1: Recall return value passing rules for 64-bit values
AAPCS specifies that 64-bit return values are passed using two registers: r0 and r1 combined.Step 2: Eliminate incorrect options
r0 alone holds 32 bits, so it cannot hold 64-bit values. Stack is not used for normal return values. r2 and r3 are not used for return values.Final Answer:
In r0 and r1 combined -> Option CQuick Check:
64-bit return uses r0 and r1 [OK]
- Assuming 64-bit fits in r0 alone
- Returning via stack unnecessarily
- Using wrong registers for return
Ready to prove it?
Pass the test and this pattern moves unknown
