What if every function call in your program was a mystery box you had to carefully open and close yourself?
Why Subroutine call convention (AAPCS) in ARM Architecture? - Purpose & Use Cases
Imagine writing a program where every time you call a small task (subroutine), you have to remember exactly which registers to save and restore yourself, and how to pass each piece of data manually.
Without a clear rulebook, your code becomes a confusing mess, and different parts of your program might not work well together.
Manually managing which registers to save or restore is slow and error-prone.
You might overwrite important data or cause crashes because one part of the program expects data in a certain place, but another part changed it unexpectedly.
This makes debugging very hard and wastes time.
The AAPCS (ARM Architecture Procedure Call Standard) sets clear rules for how subroutines should pass arguments, use registers, and return values.
This standard ensures every part of the program agrees on how to communicate, making code reliable and easier to maintain.
push {r0, r1}
mov r0, #5
bl some_function
pop {r0, r1}bl some_function ; AAPCS ensures r0-r3 used for args, r0 for return
It enables smooth, predictable communication between different parts of a program and even between different programs or libraries on ARM devices.
When your smartphone runs apps, the operating system and apps use AAPCS to call functions safely and efficiently without crashing or mixing up data.
Manual register management is complex and risky.
AAPCS provides a clear, shared set of rules for subroutine calls.
This makes ARM programs more reliable and easier to build and maintain.
Practice
Solution
Step 1: Understand argument passing in AAPCS
The AAPCS specifies that the first four arguments to a subroutine are passed using registers r0, r1, r2, and r3.Step 2: Identify the correct register range
Registers r4 to r11 are used for other purposes, and lr (link register) stores the return address, not arguments.Final Answer:
r0 to r3 -> Option AQuick Check:
Arguments passed in r0-r3 [OK]
- Confusing argument registers with callee-saved registers
- Thinking lr or pc hold arguments
- Assuming stack is always used first
Solution
Step 1: Identify the purpose of the link register (lr)
In AAPCS, the link register (lr) holds the return address when a subroutine is called.Step 2: Differentiate from other registers
r0 is for return values, pc is the program counter (current instruction), and sp is the stack pointer, not for return addresses.Final Answer:
lr -> Option AQuick Check:
Return address stored in lr [OK]
- Confusing lr with pc (program counter)
- Thinking r0 holds return address
- Assuming sp stores return address
Solution
Step 1: Recall argument passing rules for more than 4 arguments
AAPCS passes the first 4 arguments in registers r0 to r3. Any additional arguments are passed on the stack.Step 2: Apply to 5 arguments
For 5 arguments, the first 4 go into r0-r3, and the 5th argument is placed on the stack.Final Answer:
First 4 in r0 to r3, 5th on the stack -> Option BQuick Check:
Extra args beyond 4 go on stack [OK]
- Assuming all args fit in registers
- Passing 5th arg in r4 incorrectly
- Ignoring stack usage for extra args
Solution
Step 1: Understand register saving responsibilities
Under AAPCS, registers r4 to r11 are callee-saved, meaning the called function must save and restore them if it uses them.Step 2: Identify the cause of unexpected change
If r4 changed unexpectedly, it means the callee did not save and restore it properly, causing corruption.Final Answer:
r4 is a callee-saved register and the callee did not save it -> Option DQuick Check:
Callee must save r4-r11 [OK]
- Thinking r4 is caller-saved
- Confusing argument registers with saved registers
- Assuming r4 holds return address
Solution
Step 1: Recall return value passing rules for 64-bit values
AAPCS specifies that 64-bit return values are passed using two registers: r0 and r1 combined.Step 2: Eliminate incorrect options
r0 alone holds 32 bits, so it cannot hold 64-bit values. Stack is not used for normal return values. r2 and r3 are not used for return values.Final Answer:
In r0 and r1 combined -> Option CQuick Check:
64-bit return uses r0 and r1 [OK]
- Assuming 64-bit fits in r0 alone
- Returning via stack unnecessarily
- Using wrong registers for return
Ready to prove it?
Pass the test and this pattern moves unknown
