Subroutine call convention (AAPCS) in ARM Architecture - Time & Space Complexity
Analyzing the time complexity of subroutine calls helps us understand how the cost of calling functions grows as programs get larger or more complex.
We want to know how the number of instructions executed changes when calling subroutines following the ARM AAPCS rules.
Analyze the time complexity of the following ARM assembly code snippet for a subroutine call using AAPCS.
push {r4-r7, lr} // Save registers and return address
mov r0, r1 // Move argument
bl subroutine // Branch with link (call subroutine)
pop {r4-r7, pc} // Restore registers and return
This code saves registers, passes an argument, calls a subroutine, then restores registers and returns.
Identify the loops, recursion, array traversals that repeat.
- Primary operation: The subroutine call and return instructions.
- How many times: Each call executes these instructions once per call.
Each subroutine call involves a fixed number of instructions to save and restore registers and to branch.
| Input Size (number of calls) | Approx. Operations |
|---|---|
| 10 | About 10 times the fixed call instructions |
| 100 | About 100 times the fixed call instructions |
| 1000 | About 1000 times the fixed call instructions |
Pattern observation: The total instructions grow directly with the number of subroutine calls.
Time Complexity: O(n)
This means the total execution time grows linearly with the number of subroutine calls made.
[X] Wrong: "Calling a subroutine is free or constant time regardless of how many times it is called."
[OK] Correct: Each call requires saving/restoring registers and branching, so the total time increases with the number of calls.
Understanding how subroutine calls scale helps you reason about program performance and efficient use of function calls in real projects.
What if the subroutine used more registers that need saving? How would that affect the time complexity?
Practice
Solution
Step 1: Understand argument passing in AAPCS
The AAPCS specifies that the first four arguments to a subroutine are passed using registers r0, r1, r2, and r3.Step 2: Identify the correct register range
Registers r4 to r11 are used for other purposes, and lr (link register) stores the return address, not arguments.Final Answer:
r0 to r3 -> Option AQuick Check:
Arguments passed in r0-r3 [OK]
- Confusing argument registers with callee-saved registers
- Thinking lr or pc hold arguments
- Assuming stack is always used first
Solution
Step 1: Identify the purpose of the link register (lr)
In AAPCS, the link register (lr) holds the return address when a subroutine is called.Step 2: Differentiate from other registers
r0 is for return values, pc is the program counter (current instruction), and sp is the stack pointer, not for return addresses.Final Answer:
lr -> Option AQuick Check:
Return address stored in lr [OK]
- Confusing lr with pc (program counter)
- Thinking r0 holds return address
- Assuming sp stores return address
Solution
Step 1: Recall argument passing rules for more than 4 arguments
AAPCS passes the first 4 arguments in registers r0 to r3. Any additional arguments are passed on the stack.Step 2: Apply to 5 arguments
For 5 arguments, the first 4 go into r0-r3, and the 5th argument is placed on the stack.Final Answer:
First 4 in r0 to r3, 5th on the stack -> Option BQuick Check:
Extra args beyond 4 go on stack [OK]
- Assuming all args fit in registers
- Passing 5th arg in r4 incorrectly
- Ignoring stack usage for extra args
Solution
Step 1: Understand register saving responsibilities
Under AAPCS, registers r4 to r11 are callee-saved, meaning the called function must save and restore them if it uses them.Step 2: Identify the cause of unexpected change
If r4 changed unexpectedly, it means the callee did not save and restore it properly, causing corruption.Final Answer:
r4 is a callee-saved register and the callee did not save it -> Option DQuick Check:
Callee must save r4-r11 [OK]
- Thinking r4 is caller-saved
- Confusing argument registers with saved registers
- Assuming r4 holds return address
Solution
Step 1: Recall return value passing rules for 64-bit values
AAPCS specifies that 64-bit return values are passed using two registers: r0 and r1 combined.Step 2: Eliminate incorrect options
r0 alone holds 32 bits, so it cannot hold 64-bit values. Stack is not used for normal return values. r2 and r3 are not used for return values.Final Answer:
In r0 and r1 combined -> Option CQuick Check:
64-bit return uses r0 and r1 [OK]
- Assuming 64-bit fits in r0 alone
- Returning via stack unnecessarily
- Using wrong registers for return
Ready to prove it?
Pass the test and this pattern moves unknown
