PendSV and SysTick exceptions in ARM Architecture - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to identify the exception used for system tick timer interrupts.

ARM Architecture

void SysTick_Handler(void) {
    // This function handles the [1] exception
}

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ASysTick

BPendSV

CHardFault

DNMI

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing PendSV with SysTick exception.

Using HardFault or NMI which are unrelated to system tick timer.

The SysTick exception is triggered by the system timer to generate periodic interrupts.

2fill in blank

medium

Complete the sentence to describe the purpose of the PendSV exception.

ARM Architecture

The PendSV exception is mainly used for [1] in ARM Cortex-M processors.

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Aresetting the processor

Bsystem tick timing

Cerror handling

Dcontext switching

Attempts:

3 left

💡 Hint

Common Mistakes

Thinking PendSV handles system tick timing.

Confusing PendSV with reset or error exceptions.

PendSV is designed to handle context switching in operating systems on ARM Cortex-M.

3fill in blank

hard

Fix the error in the description of SysTick and PendSV exceptions.

ARM Architecture

SysTick is used for [1] while PendSV is used for system tick timing.

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Asystem tick timing

Bresetting

Ccontext switching

Derror handling

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping the roles of SysTick and PendSV.

Assuming PendSV handles timer interrupts.

SysTick is used for system tick timing, while PendSV is used for context switching.

4fill in blank

hard

Fill both blanks to complete the statement about exception priorities.

ARM Architecture

In ARM Cortex-M, the [1] exception usually has lower priority than the [2] exception.

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APendSV

BSysTick

CHardFault

DNMI

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning PendSV higher priority than SysTick.

Confusing HardFault or NMI with these exceptions.

PendSV is typically assigned a lower priority than SysTick to allow SysTick interrupts to preempt PendSV.

5fill in blank

hard

Fill all three blanks to complete the dictionary literal that maps exception names to their typical uses.

ARM Architecture

exception_uses = {
    "SysTick": "[1]",
    "PendSV": "[2]",
    "HardFault": "[3]"
}

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Asystem tick timer

Bcontext switching

Cerror handling

Dresetting

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up the uses of these exceptions.

Assigning resetting to HardFault instead of error handling.

SysTick is for system tick timer interrupts, PendSV for context switching, and HardFault for error handling.

Practice

1. What is the primary purpose of the PendSV exception in ARM processors?

easy

A. To reset the processor

B. To provide a regular timer interrupt

C. To handle task switching smoothly in the background

D. To manage memory access

Solution

1. Step 1: Understand PendSV role

   PendSV is designed to handle context switching between tasks without interrupting the main program flow.

2. Step 2: Compare with other exceptions

   Unlike SysTick, which provides timing interrupts, PendSV is specifically for smooth task switching.

3. Final Answer:

   To handle task switching smoothly in the background -> Option C

4. Quick Check:

   PendSV = task switching [OK]

Hint: PendSV = background task switcher [OK]

Common Mistakes:

• Confusing PendSV with SysTick timer
• Thinking PendSV resets the processor
• Assuming PendSV manages memory

2. Which of the following is the correct way to enable the SysTick timer in ARM Cortex-M processors?

easy

A. Set the CTRL register's ENABLE bit to 1

B. Clear the CTRL register's ENABLE bit to 0

C. Write 0xFFFFFFFF to the LOAD register

D. Disable the PendSV exception

Solution

1. Step 1: Identify SysTick control

   The SysTick timer is controlled by the CTRL register, where setting the ENABLE bit starts the timer.

2. Step 2: Eliminate incorrect options

   Clearing ENABLE stops the timer, writing max to LOAD sets reload value but doesn't enable, and disabling PendSV is unrelated.

3. Final Answer:

   Set the CTRL register's ENABLE bit to 1 -> Option A

4. Quick Check:

   SysTick enable = CTRL ENABLE bit set [OK]

Hint: Enable SysTick by setting CTRL ENABLE bit [OK]

Common Mistakes:

• Confusing enabling with disabling bits
• Thinking LOAD register enables timer
• Mixing PendSV control with SysTick

3. Consider this simplified ARM Cortex-M code snippet:

SysTick->LOAD = 1000 - 1;
SysTick->VAL = 0;
SysTick->CTRL = 7;

What does the value 7 in SysTick->CTRL represent?

medium

A. Enable SysTick, enable interrupt, and use processor clock

B. Disable SysTick and interrupts

C. Enable SysTick only without interrupts

D. Reset SysTick counter

Solution

1. Step 1: Decode CTRL register bits

   Value 7 in binary is 0b111, meaning bits ENABLE(0), TICKINT(1), and CLKSOURCE(2) are set.

2. Step 2: Understand each bit meaning

   ENABLE starts the timer, TICKINT enables interrupt, CLKSOURCE selects processor clock.

3. Final Answer:

   Enable SysTick, enable interrupt, and use processor clock -> Option A

4. Quick Check:

   CTRL=7 means all three bits set [OK]

Hint: 7 in CTRL means enable + interrupt + clock source [OK]

Common Mistakes:

• Ignoring interrupt enable bit
• Assuming 7 disables timer
• Confusing bits order

4. A developer writes this code to trigger PendSV manually:

SCB->ICSR |= (1 << 28);

But the PendSV exception does not occur. What is the likely cause?

medium

A. ICSR register is read-only

B. SysTick timer is disabled

C. PendSV cannot be triggered manually

D. PendSV priority is not set low enough

Solution

1. Step 1: Understand PendSV triggering

   Writing to ICSR bit 28 sets the PendSV pending flag, but PendSV only runs if its priority is low enough.

2. Step 2: Identify common mistake

   If PendSV priority is higher or equal to other interrupts, it won't run even if pending.

3. Final Answer:

   PendSV priority is not set low enough -> Option D

4. Quick Check:

   PendSV priority must be low to run [OK]

Hint: PendSV needs low priority to run when pending [OK]

Common Mistakes:

• Assuming ICSR is read-only
• Thinking SysTick affects PendSV trigger
• Believing PendSV can't be triggered manually

5. In a real-time operating system (RTOS) on ARM Cortex-M, how do PendSV and SysTick work together to manage multitasking?

hard

A. PendSV triggers timer interrupts; SysTick switches tasks

B. SysTick triggers regular interrupts; PendSV performs context switching after SysTick

C. Both PendSV and SysTick handle memory management

D. SysTick disables PendSV during task switching

Solution

1. Step 1: Understand SysTick role in RTOS

   SysTick generates periodic interrupts to keep track of time slices and trigger scheduler checks.

2. Step 2: Understand PendSV role in RTOS

   PendSV is triggered by the scheduler to perform the actual task context switch smoothly in the background.

3. Step 3: Combine roles for multitasking

   SysTick signals when to switch; PendSV does the switch, enabling efficient multitasking.

4. Final Answer:

   SysTick triggers regular interrupts; PendSV performs context switching after SysTick -> Option B

5. Quick Check:

   SysTick = timer, PendSV = switcher [OK]

Hint: SysTick triggers; PendSV switches tasks [OK]

Common Mistakes:

• Swapping roles of PendSV and SysTick
• Thinking both handle memory
• Assuming SysTick disables PendSV