PendSV and SysTick exceptions in ARM Architecture - Mini Project: Build & Apply

Understanding PendSV and SysTick Exceptions in ARM Architecture

📖 Scenario: You are learning about ARM Cortex processors and how they handle special system events called exceptions. Two important exceptions are PendSV and SysTick. These help the processor manage tasks and keep time.Imagine you are building a simple system that uses these exceptions to switch tasks and keep track of time.

🎯 Goal: Create a basic setup that defines the PendSV and SysTick exceptions, configure a timer for SysTick, and write simple handlers to understand how these exceptions work together in ARM Cortex processors.

📋 What You'll Learn

Define the PendSV exception handler function named PendSV_Handler

Define the SysTick exception handler function named SysTick_Handler

Create a variable tick_count to count SysTick interrupts

Configure the SysTick timer with a reload value of 1000

Enable the SysTick timer and its interrupt

💡 Why This Matters

🌍 Real World

PendSV and SysTick exceptions are used in real-time operating systems on ARM Cortex processors to manage task switching and system timing.

💼 Career

Understanding these exceptions is important for embedded systems developers working on ARM Cortex microcontrollers, especially in firmware and RTOS development.

1

Define the PendSV and SysTick exception handlers

Write two empty functions named PendSV_Handler and SysTick_Handler to represent the PendSV and SysTick exception handlers.

ARM Architecture

# Define the PendSV_Handler function
# Define the SysTick_Handler function
# Your code here

Hint

Use the exact function names PendSV_Handler and SysTick_Handler with void return type and no parameters.

2

Create a tick counter variable

Declare a global variable named tick_count of type unsigned int and initialize it to 0. This will count the number of SysTick interrupts.

ARM Architecture

void PendSV_Handler(void) {
    // PendSV exception handler code will go here
}

void SysTick_Handler(void) {
    // SysTick exception handler code will go here
}

// Declare tick_count variable
# Your code here

Hint

Use unsigned int tick_count = 0; exactly as shown.

3

Implement SysTick_Handler to increment tick_count

Inside the SysTick_Handler function, add code to increase the tick_count variable by 1 each time the SysTick exception occurs.

ARM Architecture

unsigned int tick_count = 0;

void PendSV_Handler(void) {
    // PendSV exception handler code will go here
}

void SysTick_Handler(void) {
    // Increment tick_count here
    # Your code here
}

Hint

Inside SysTick_Handler, write tick_count++; to increase the counter.

4

Configure and enable the SysTick timer

Write code to set the SysTick reload value to 1000, clear the current value, and enable the SysTick timer with its interrupt. Use the exact variable names SysTick->LOAD, SysTick->VAL, and SysTick->CTRL. Set SysTick->CTRL to 0x07 to enable the timer, its interrupt, and the processor clock.

ARM Architecture

unsigned int tick_count = 0;

void PendSV_Handler(void) {
    // PendSV exception handler code will go here
}

void SysTick_Handler(void) {
    tick_count++;
}

// Configure SysTick timer
# Your code here

Hint

Set SysTick->LOAD to 1000, clear SysTick->VAL, and set SysTick->CTRL to 0x07 to enable timer, interrupt, and clock.

Practice

1. What is the primary purpose of the PendSV exception in ARM processors?

easy

A. To reset the processor

B. To provide a regular timer interrupt

C. To handle task switching smoothly in the background

D. To manage memory access

Solution

1. Step 1: Understand PendSV role

   PendSV is designed to handle context switching between tasks without interrupting the main program flow.

2. Step 2: Compare with other exceptions

   Unlike SysTick, which provides timing interrupts, PendSV is specifically for smooth task switching.

3. Final Answer:

   To handle task switching smoothly in the background -> Option C

4. Quick Check:

   PendSV = task switching [OK]

Hint: PendSV = background task switcher [OK]

Common Mistakes:

• Confusing PendSV with SysTick timer
• Thinking PendSV resets the processor
• Assuming PendSV manages memory

2. Which of the following is the correct way to enable the SysTick timer in ARM Cortex-M processors?

easy

A. Set the CTRL register's ENABLE bit to 1

B. Clear the CTRL register's ENABLE bit to 0

C. Write 0xFFFFFFFF to the LOAD register

D. Disable the PendSV exception

Solution

1. Step 1: Identify SysTick control

   The SysTick timer is controlled by the CTRL register, where setting the ENABLE bit starts the timer.

2. Step 2: Eliminate incorrect options

   Clearing ENABLE stops the timer, writing max to LOAD sets reload value but doesn't enable, and disabling PendSV is unrelated.

3. Final Answer:

   Set the CTRL register's ENABLE bit to 1 -> Option A

4. Quick Check:

   SysTick enable = CTRL ENABLE bit set [OK]

Hint: Enable SysTick by setting CTRL ENABLE bit [OK]

Common Mistakes:

• Confusing enabling with disabling bits
• Thinking LOAD register enables timer
• Mixing PendSV control with SysTick

3. Consider this simplified ARM Cortex-M code snippet:

SysTick->LOAD = 1000 - 1;
SysTick->VAL = 0;
SysTick->CTRL = 7;

What does the value 7 in SysTick->CTRL represent?

medium

A. Enable SysTick, enable interrupt, and use processor clock

B. Disable SysTick and interrupts

C. Enable SysTick only without interrupts

D. Reset SysTick counter

Solution

1. Step 1: Decode CTRL register bits

   Value 7 in binary is 0b111, meaning bits ENABLE(0), TICKINT(1), and CLKSOURCE(2) are set.

2. Step 2: Understand each bit meaning

   ENABLE starts the timer, TICKINT enables interrupt, CLKSOURCE selects processor clock.

3. Final Answer:

   Enable SysTick, enable interrupt, and use processor clock -> Option A

4. Quick Check:

   CTRL=7 means all three bits set [OK]

Hint: 7 in CTRL means enable + interrupt + clock source [OK]

Common Mistakes:

• Ignoring interrupt enable bit
• Assuming 7 disables timer
• Confusing bits order

4. A developer writes this code to trigger PendSV manually:

SCB->ICSR |= (1 << 28);

But the PendSV exception does not occur. What is the likely cause?

medium

A. ICSR register is read-only

B. SysTick timer is disabled

C. PendSV cannot be triggered manually

D. PendSV priority is not set low enough

Solution

1. Step 1: Understand PendSV triggering

   Writing to ICSR bit 28 sets the PendSV pending flag, but PendSV only runs if its priority is low enough.

2. Step 2: Identify common mistake

   If PendSV priority is higher or equal to other interrupts, it won't run even if pending.

3. Final Answer:

   PendSV priority is not set low enough -> Option D

4. Quick Check:

   PendSV priority must be low to run [OK]

Hint: PendSV needs low priority to run when pending [OK]

Common Mistakes:

• Assuming ICSR is read-only
• Thinking SysTick affects PendSV trigger
• Believing PendSV can't be triggered manually

5. In a real-time operating system (RTOS) on ARM Cortex-M, how do PendSV and SysTick work together to manage multitasking?

hard

A. PendSV triggers timer interrupts; SysTick switches tasks

B. SysTick triggers regular interrupts; PendSV performs context switching after SysTick

C. Both PendSV and SysTick handle memory management

D. SysTick disables PendSV during task switching

Solution

1. Step 1: Understand SysTick role in RTOS

   SysTick generates periodic interrupts to keep track of time slices and trigger scheduler checks.

2. Step 2: Understand PendSV role in RTOS

   PendSV is triggered by the scheduler to perform the actual task context switch smoothly in the background.

3. Step 3: Combine roles for multitasking

   SysTick signals when to switch; PendSV does the switch, enabling efficient multitasking.

4. Final Answer:

   SysTick triggers regular interrupts; PendSV performs context switching after SysTick -> Option B

5. Quick Check:

   SysTick = timer, PendSV = switcher [OK]

Hint: SysTick triggers; PendSV switches tasks [OK]

Common Mistakes:

• Swapping roles of PendSV and SysTick
• Thinking both handle memory
• Assuming SysTick disables PendSV