You want to ensure that a critical sensor interrupt always preempts a less important communication interrupt. How should you configure NVIC priorities for SENSOR_IRQn and COMM_IRQn?

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ARM Architecture - Exception and Interrupt Model

You want to ensure that a critical sensor interrupt always preempts a less important communication interrupt. How should you configure NVIC priorities for SENSOR_IRQn and COMM_IRQn?

ASet SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1)

BSet SENSOR_IRQn priority higher than COMM_IRQn (e.g., SENSOR=2, COMM=1)

CDisable COMM_IRQn and enable SENSOR_IRQn only

DSet both priorities equal and enable both

Step-by-Step Solution

Solution:

Step 1: Recall NVIC priority rules
Lower numeric priority means higher priority and can preempt others.
Step 2: Apply to SENSOR and COMM interrupts
To let SENSOR_IRQn preempt COMM_IRQn, SENSOR_IRQn must have a lower priority number.
Final Answer:
Set SENSOR_IRQn priority lower than COMM_IRQn (e.g., SENSOR=0, COMM=1) -> Option A
Quick Check:
Lower number = higher priority = SENSOR_IRQn preempts [OK]

Quick Trick: Lower priority number means higher interrupt priority [OK]

Common Mistakes:

Assigning higher number for higher priority
Disabling interrupts instead of prioritizing
Setting equal priorities expecting preemption

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More ARM Architecture Quizzes

You want to ensure that a critical sensor interrupt always preempts a less important communication interrupt. How should you configure NVIC priorities for SENSOR_IRQn and COMM_IRQn?

Step 1: Recall NVIC priority rules

Step 2: Apply to SENSOR and COMM interrupts

Final Answer:

Quick Check:

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