[Solved] A developer tries this sequence: MRS R0, SCR BIC R0, R0, #0x4 MSR SCR, R0 WFI What is the effect of clearing bit 2 (0x4) before WFI? | ARM Architecture

ARM Architecture - Power Modes

A developer tries this sequence:

    MRS R0, SCR
    BIC R0, R0, #0x4
    MSR SCR, R0
    WFI

What is the effect of clearing bit 2 (0x4) before WFI?

ACPU triggers a reset

BCPU enters deep sleep mode

CCPU enters normal sleep mode, not deep sleep

DCPU ignores the WFI instruction

Step-by-Step Solution

Solution:

Step 1: Understand BIC instruction effect
BIC clears specified bits; here it clears SLEEPDEEP bit (0x4).
Step 2: Result of clearing SLEEPDEEP bit
Clearing SLEEPDEEP means CPU will enter normal sleep mode on WFI.
Final Answer:
CPU enters normal sleep mode, not deep sleep -> Option C
Quick Check:
Cleared SLEEPDEEP = normal sleep = A [OK]

Quick Trick: Clearing SLEEPDEEP bit disables deep sleep [OK]

Common Mistakes:

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