ARM Architecture - Exception and Interrupt Model
Consider the following code snippet for ARM Cortex-M NVIC:
NVIC_SetPriority(TIM2_IRQn, 2); NVIC_EnableIRQ(TIM2_IRQn); NVIC_SetPriority(USART1_IRQn, 1); NVIC_EnableIRQ(USART1_IRQn);Which interrupt has higher priority?
