NVIC advanced features in ARM Architecture - Step-by-Step Execution

Concept Flow - NVIC advanced features

Interrupt Request

↓

NVIC Receives IRQ

↓

Check Priority Grouping

↓

Determine Preemption Priority

↓

Determine Subpriority

↓

Check Pending and Enable Flags

↓

Preempt Lower Priority Interrupt?

Yes→Switch Context

↓

Execute ISR

↓

Execute ISR if Enabled

↓

Clear Pending Flag

↓

Return to Main Program

This flow shows how NVIC handles interrupts using priority grouping, preemption, and subpriority to decide which interrupt to execute.

Execution Sample

ARM Architecture

1. IRQ occurs
2. NVIC checks priority grouping
3. NVIC compares preemption priorities
4. NVIC compares subpriorities
5. NVIC decides to preempt or not
6. ISR executes

This sequence shows how NVIC processes an interrupt request considering advanced priority features.

Analysis Table

Step	Action	Priority Grouping	Preemption Priority	Subpriority	Decision	Result
1	IRQ from peripheral A	Group 2	2	1	N/A	IRQ received
2	IRQ from peripheral B	Group 2	1	3	Compare with A	B has higher preemption priority
3	Check if B can preempt A	Group 2	1 vs 2	N/A	Yes	Switch to B ISR
4	Execute ISR for B	Group 2	1	3	N/A	ISR B running
5	IRQ from peripheral C	Group 2	2	0	Compare with B	B has higher preemption priority
6	Check if C can preempt B	Group 2	2 vs 1	N/A	No	C waits
7	ISR B completes	Group 2	1	3	N/A	Return to main or pending ISR
8	Execute ISR for C	Group 2	2	0	N/A	ISR C running
9	Clear pending flags	Group 2	N/A	N/A	N/A	Interrupts cleared
10	Return to main program	Group 2	N/A	N/A	N/A	Normal execution resumes

💡 Execution stops after all pending interrupts are handled and control returns to main program.

State Tracker

Variable	Start	After Step 1	After Step 3	After Step 6	After Step 8	Final
Current IRQ	None	Peripheral A	Peripheral B	Peripheral B	Peripheral C	None
Preemption Priority	N/A	2	1	1	2	N/A
Subpriority	N/A	1	3	3	0	N/A
ISR Running	None	None	ISR B	ISR B	ISR C	None
Pending IRQs	None	None	Peripheral A	Peripheral A, C	Peripheral A	None

Key Insights - 3 Insights

Why does peripheral B preempt peripheral A even though A's interrupt came first?

Because peripheral B has a higher preemption priority (1) compared to A (2), NVIC allows B to preempt A as shown in execution_table step 3.

Why can't peripheral C preempt peripheral B even though C has a lower subpriority?

Preemption depends first on preemption priority, not subpriority. Since C's preemption priority (2) is lower than B's (1), C cannot preempt B (execution_table step 6).

What happens to pending interrupts when a higher priority ISR is running?

Lower priority interrupts remain pending and wait until the higher priority ISR completes, as shown by pending IRQs in variable_tracker after step 6.

Visual Quiz - 3 Questions

Look at the execution_table at step 3. What decision does NVIC make?

A Both interrupts run simultaneously

B Peripheral A continues running

C Peripheral B preempts Peripheral A

D NVIC ignores Peripheral B

💡 Hint

Refer to execution_table row with Step 3 showing 'Switch to B ISR'

At which step does Peripheral C start executing its ISR?

A Step 8

B Step 6

C Step 5

D Step 9

💡 Hint

Check execution_table row where 'ISR C running' is noted

If Peripheral C had a preemption priority of 0, what would change in the execution_table?

A Peripheral C would still wait

B Peripheral C would preempt Peripheral B at step 6

C Peripheral A would preempt Peripheral B

D No interrupts would run

💡 Hint

Compare preemption priorities in execution_table steps 3 and 6

Concept Snapshot

NVIC Advanced Features:
- Uses priority grouping to split priority into preemption and subpriority
- Preemption priority decides if an interrupt can interrupt another
- Subpriority resolves tie-breaks when preemption priorities are equal
- NVIC manages pending and active interrupts based on these priorities
- Higher preemption priority interrupts can preempt lower ones
- Subpriority only affects order when preemption priorities match

Full Transcript

The NVIC (Nested Vectored Interrupt Controller) advanced features manage multiple interrupts by using priority grouping. This splits the priority into preemption priority and subpriority. When an interrupt request (IRQ) occurs, NVIC compares the preemption priorities of active and pending interrupts. If a new interrupt has a higher preemption priority, it can preempt the currently running interrupt service routine (ISR). If preemption priorities are equal, subpriority determines which interrupt runs first. Lower priority interrupts remain pending until higher priority ISRs complete. This system ensures efficient and predictable interrupt handling in ARM Cortex-M processors.

Practice

1. What is the main purpose of the NVIC's priority grouping feature?

easy

A. To disable all interrupts at once

B. To balance between pre-emption priority and subpriority levels

C. To increase the clock speed of the processor

D. To reset the microcontroller

Solution

1. Step 1: Understand NVIC priority grouping

   Priority grouping allows dividing interrupt priority into pre-emption priority and subpriority.

2. Step 2: Identify the purpose of balancing priorities

   This balance controls which interrupts can pre-empt others and which are handled in order if priorities are equal.

3. Final Answer:

   To balance between pre-emption priority and subpriority levels -> Option B

4. Quick Check:

   Priority grouping = Balancing priorities [OK]

Hint: Priority grouping splits interrupt priority levels [OK]

Common Mistakes:

• Confusing priority grouping with disabling interrupts
• Thinking it changes processor speed
• Assuming it resets the device

2. Which of the following is the correct way to enable an interrupt in NVIC?

easy

A. NVIC_DisableIRQ(IRQn);

B. NVIC_SetPriority(IRQn, priority);

C. NVIC_EnableIRQ(IRQn);

D. NVIC_ClearPendingIRQ(IRQn);

Solution

1. Step 1: Identify function to enable interrupts

   The function NVIC_EnableIRQ(IRQn) is used to enable a specific interrupt.

2. Step 2: Differentiate from other NVIC functions

   NVIC_DisableIRQ disables interrupts, SetPriority sets priority, ClearPendingIRQ clears pending flags.

3. Final Answer:

   NVIC_EnableIRQ(IRQn); -> Option C

4. Quick Check:

   Enable interrupt = NVIC_EnableIRQ [OK]

Hint: Enable interrupts with NVIC_EnableIRQ function [OK]

Common Mistakes:

• Using NVIC_DisableIRQ to enable interrupts
• Confusing priority setting with enabling
• Clearing pending interrupts instead of enabling

3. Consider the following code snippet:

NVIC_SetPriorityGrouping(3);
NVIC_SetPriority(IRQn, NVIC_EncodePriority(3, 1, 2));

What does this code do?

medium

A. Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn

B. Disables IRQn interrupt

C. Enables IRQn interrupt with default priority

D. Resets priority grouping to default

Solution

1. Step 1: Analyze NVIC_SetPriorityGrouping(3)

   This sets the priority grouping to 3, defining how many bits are for pre-emption and subpriority.

2. Step 2: Decode NVIC_SetPriority call

   NVIC_EncodePriority(3, 1, 2) encodes pre-emption priority 1 and subpriority 2 according to grouping 3, then assigns it to IRQn.

3. Final Answer:

   Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn -> Option A

4. Quick Check:

   Priority grouping 3 + encoded priority = Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn [OK]

Hint: Priority grouping affects encoding of priorities [OK]

Common Mistakes:

• Assuming it disables or enables interrupts
• Ignoring priority encoding details
• Confusing priority grouping with resetting

4. A developer wrote this code to disable an interrupt but it does not work:

NVIC_EnableIRQ(IRQn);

What is the error?

medium

A. The function NVIC_EnableIRQ enables, not disables, interrupts

B. IRQn is not a valid interrupt number

C. NVIC_DisableIRQ should be called before NVIC_EnableIRQ

D. Priority must be set before disabling interrupts

Solution

1. Step 1: Understand function purpose

   NVIC_EnableIRQ enables the interrupt, so using it to disable is incorrect.

2. Step 2: Identify correct function to disable

   NVIC_DisableIRQ should be used to disable interrupts, not NVIC_EnableIRQ.

3. Final Answer:

   The function NVIC_EnableIRQ enables, not disables, interrupts -> Option A

4. Quick Check:

   EnableIRQ enables, not disables [OK]

Hint: EnableIRQ enables; use DisableIRQ to disable [OK]

Common Mistakes:

• Confusing enable and disable functions
• Assuming priority affects enabling/disabling
• Thinking order of calls disables interrupts

5. You want to ensure that a critical interrupt always pre-empts others regardless of subpriority. Which NVIC configuration achieves this?

hard

A. Use NVIC_DisableIRQ on all other interrupts

B. Set all interrupts to the same priority level

C. Disable subpriority by setting it to maximum value

D. Set priority grouping to allocate all bits to pre-emption priority and zero to subpriority

Solution

1. Step 1: Understand priority grouping effect

   Setting priority grouping to allocate all bits to pre-emption priority means subpriority is zero, so pre-emption controls interrupt order fully.

2. Step 2: Confirm this ensures critical interrupt pre-empts others

   With no subpriority bits, the critical interrupt's pre-emption priority dominates, allowing it to always pre-empt.

3. Final Answer:

   Set priority grouping to allocate all bits to pre-emption priority and zero to subpriority -> Option D

4. Quick Check:

   All bits to pre-emption priority = critical pre-emption [OK]

Hint: Maximize pre-emption bits to ensure critical interrupt priority [OK]

Common Mistakes:

• Thinking disabling subpriority means setting it high
• Assuming same priority levels allow pre-emption
• Disabling other interrupts is not practical