NVIC advanced features in ARM Architecture - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to enable an interrupt in the NVIC.

ARM Architecture

NVIC->ISER[0] = 1 << [1];

Drag options to blanks, or click blank then click option'

A10

B5

C3

D15

Attempts:

3 left

💡 Hint

Common Mistakes

Using the interrupt number directly without shifting.

Shifting by an incorrect interrupt number.

The NVIC Interrupt Set-Enable Register (ISER) uses the bit position to enable the corresponding interrupt number. Shifting 1 by 3 enables interrupt number 3.

2fill in blank

medium

Complete the code to set the priority of interrupt 7 in the NVIC.

ARM Architecture

NVIC->IP[[1]] = 0x40;

Drag options to blanks, or click blank then click option'

A7

B5

C3

D10

Attempts:

3 left

💡 Hint

Common Mistakes

Using the wrong index for the interrupt priority.

Confusing priority value with interrupt number.

The NVIC Interrupt Priority Register (IP) array uses the interrupt number as the index. Setting IP[7] assigns priority to interrupt 7.

3fill in blank

hard

Fix the error in the code to clear a pending interrupt in the NVIC.

ARM Architecture

NVIC->ICPR[0] = 1 << [1];

Drag options to blanks, or click blank then click option'

A32

B8

C31

D16

Attempts:

3 left

💡 Hint

Common Mistakes

Using an interrupt number outside the valid range.

Shifting by 32 which is invalid for a 32-bit register.

The Interrupt Clear-Pending Register (ICPR) uses bits 0-31 for interrupts 0-31. Shifting 1 by 8 clears pending interrupt 8. Shifting by 32 is invalid as it exceeds 31.

4fill in blank

hard

Fill both blanks to configure the priority grouping in the NVIC.

ARM Architecture

NVIC_SetPriorityGrouping([1]);
SCB->AIRCR = (0x5FA << 16) | ([2] << 8);

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ANVIC_PRIORITYGROUP_3

BNVIC_PRIORITYGROUP_4

CNVIC_PRIORITYGROUP_2

DNVIC_PRIORITYGROUP_1

Attempts:

3 left

💡 Hint

Common Mistakes

Using mismatched priority grouping values in the function and AIRCR.

Forgetting the key (0x5FA) in AIRCR write.

NVIC_SetPriorityGrouping configures how many bits are used for pre-emption priority and subpriority. The AIRCR register must be written with the key (0x5FA) and the priority grouping value shifted to bits 10:8. Using NVIC_PRIORITYGROUP_3 consistently sets this grouping.

5fill in blank

hard

Fill all three blanks to create a dictionary comprehension that maps interrupt numbers to their enabled status in NVIC.

ARM Architecture

enabled_interrupts = [1]: (NVIC->ISER[0] & (1 << [2])) != 0 for [3] in range(32)

Drag options to blanks, or click blank then click option'

Ai

Bx

Cinterrupt

Dnum

Attempts:

3 left

💡 Hint

Common Mistakes

Using different variable names in key and loop causing syntax errors.

Using a variable name not defined in the for loop.

This comprehension creates a dictionary where each key is an interrupt number (named 'interrupt') and the value is True if that interrupt is enabled in NVIC->ISER[0]. Using the same variable name 'interrupt' consistently is required for correct comprehension syntax.

Practice

1. What is the main purpose of the NVIC's priority grouping feature?

easy

A. To disable all interrupts at once

B. To balance between pre-emption priority and subpriority levels

C. To increase the clock speed of the processor

D. To reset the microcontroller

Solution

1. Step 1: Understand NVIC priority grouping

   Priority grouping allows dividing interrupt priority into pre-emption priority and subpriority.

2. Step 2: Identify the purpose of balancing priorities

   This balance controls which interrupts can pre-empt others and which are handled in order if priorities are equal.

3. Final Answer:

   To balance between pre-emption priority and subpriority levels -> Option B

4. Quick Check:

   Priority grouping = Balancing priorities [OK]

Hint: Priority grouping splits interrupt priority levels [OK]

Common Mistakes:

• Confusing priority grouping with disabling interrupts
• Thinking it changes processor speed
• Assuming it resets the device

2. Which of the following is the correct way to enable an interrupt in NVIC?

easy

A. NVIC_DisableIRQ(IRQn);

B. NVIC_SetPriority(IRQn, priority);

C. NVIC_EnableIRQ(IRQn);

D. NVIC_ClearPendingIRQ(IRQn);

Solution

1. Step 1: Identify function to enable interrupts

   The function NVIC_EnableIRQ(IRQn) is used to enable a specific interrupt.

2. Step 2: Differentiate from other NVIC functions

   NVIC_DisableIRQ disables interrupts, SetPriority sets priority, ClearPendingIRQ clears pending flags.

3. Final Answer:

   NVIC_EnableIRQ(IRQn); -> Option C

4. Quick Check:

   Enable interrupt = NVIC_EnableIRQ [OK]

Hint: Enable interrupts with NVIC_EnableIRQ function [OK]

Common Mistakes:

• Using NVIC_DisableIRQ to enable interrupts
• Confusing priority setting with enabling
• Clearing pending interrupts instead of enabling

3. Consider the following code snippet:

NVIC_SetPriorityGrouping(3);
NVIC_SetPriority(IRQn, NVIC_EncodePriority(3, 1, 2));

What does this code do?

medium

A. Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn

B. Disables IRQn interrupt

C. Enables IRQn interrupt with default priority

D. Resets priority grouping to default

Solution

1. Step 1: Analyze NVIC_SetPriorityGrouping(3)

   This sets the priority grouping to 3, defining how many bits are for pre-emption and subpriority.

2. Step 2: Decode NVIC_SetPriority call

   NVIC_EncodePriority(3, 1, 2) encodes pre-emption priority 1 and subpriority 2 according to grouping 3, then assigns it to IRQn.

3. Final Answer:

   Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn -> Option A

4. Quick Check:

   Priority grouping 3 + encoded priority = Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn [OK]

Hint: Priority grouping affects encoding of priorities [OK]

Common Mistakes:

• Assuming it disables or enables interrupts
• Ignoring priority encoding details
• Confusing priority grouping with resetting

4. A developer wrote this code to disable an interrupt but it does not work:

NVIC_EnableIRQ(IRQn);

What is the error?

medium

A. The function NVIC_EnableIRQ enables, not disables, interrupts

B. IRQn is not a valid interrupt number

C. NVIC_DisableIRQ should be called before NVIC_EnableIRQ

D. Priority must be set before disabling interrupts

Solution

1. Step 1: Understand function purpose

   NVIC_EnableIRQ enables the interrupt, so using it to disable is incorrect.

2. Step 2: Identify correct function to disable

   NVIC_DisableIRQ should be used to disable interrupts, not NVIC_EnableIRQ.

3. Final Answer:

   The function NVIC_EnableIRQ enables, not disables, interrupts -> Option A

4. Quick Check:

   EnableIRQ enables, not disables [OK]

Hint: EnableIRQ enables; use DisableIRQ to disable [OK]

Common Mistakes:

• Confusing enable and disable functions
• Assuming priority affects enabling/disabling
• Thinking order of calls disables interrupts

5. You want to ensure that a critical interrupt always pre-empts others regardless of subpriority. Which NVIC configuration achieves this?

hard

A. Use NVIC_DisableIRQ on all other interrupts

B. Set all interrupts to the same priority level

C. Disable subpriority by setting it to maximum value

D. Set priority grouping to allocate all bits to pre-emption priority and zero to subpriority

Solution

1. Step 1: Understand priority grouping effect

   Setting priority grouping to allocate all bits to pre-emption priority means subpriority is zero, so pre-emption controls interrupt order fully.

2. Step 2: Confirm this ensures critical interrupt pre-empts others

   With no subpriority bits, the critical interrupt's pre-emption priority dominates, allowing it to always pre-empt.

3. Final Answer:

   Set priority grouping to allocate all bits to pre-emption priority and zero to subpriority -> Option D

4. Quick Check:

   All bits to pre-emption priority = critical pre-emption [OK]

Hint: Maximize pre-emption bits to ensure critical interrupt priority [OK]

Common Mistakes:

• Thinking disabling subpriority means setting it high
• Assuming same priority levels allow pre-emption
• Disabling other interrupts is not practical