NVIC advanced features in ARM Architecture - Practice Problems & Coding Challenges

Challenge - 5 Problems

🧠 Conceptual

intermediate

Understanding NVIC Priority Grouping

In ARM Cortex-M processors, the Nested Vectored Interrupt Controller (NVIC) supports priority grouping. What is the main purpose of priority grouping in NVIC?

A To assign fixed priority levels to all interrupts without any nesting capability

B To enable interrupts only from specific peripherals while masking others

C To disable all interrupts globally during critical code sections

D To divide interrupt priority levels into pre-emption priority and subpriority to control interrupt nesting and tail-chaining

💡 Hint

Think about how NVIC manages which interrupt can interrupt another.

Priority grouping splits the priority field into pre-emption priority and subpriority bits. Pre-emption priority controls if an interrupt can preempt another, while subpriority controls ordering when two interrupts have the same pre-emption priority. This allows fine control over interrupt nesting and tail-chaining.

📋 Factual

intermediate

NVIC Interrupt Enable Registers

Which NVIC register is used to enable a specific interrupt line in ARM Cortex-M processors?

A NVIC_STIR (Software Trigger Interrupt Register)

B NVIC_ISER (Interrupt Set-Enable Register)

C NVIC_IPR (Interrupt Priority Register)

D NVIC_ICER (Interrupt Clear-Enable Register)

💡 Hint

Look for the register that sets or enables interrupts.

NVIC_ISER is used to enable interrupts by setting bits corresponding to interrupt lines. NVIC_ICER disables interrupts, NVIC_IPR sets priority, and NVIC_STIR triggers interrupts by software.

🔍 Analysis

advanced

Effect of Changing Priority Grouping

Consider an NVIC priority grouping configuration with 3 bits for pre-emption priority and 1 bit for subpriority. If this grouping is changed to 2 bits for pre-emption priority and 2 bits for subpriority, what is the main effect on interrupt behavior?

A Interrupts can nest less deeply but have finer ordering among same pre-emption priority interrupts

B Interrupts can nest more deeply and have coarser ordering among same pre-emption priority interrupts

C Interrupt nesting and ordering remain unchanged

D All interrupts become disabled until reset

💡 Hint

Think about how reducing pre-emption bits affects nesting depth and subpriority bits affect ordering.

Reducing pre-emption priority bits from 3 to 2 reduces the number of levels that can preempt each other, so nesting depth decreases. Increasing subpriority bits from 1 to 2 allows finer ordering among interrupts with the same pre-emption priority.

❓ Reasoning

advanced

NVIC Tail-Chaining Behavior

What is the benefit of NVIC tail-chaining when multiple interrupts occur back-to-back?

A It reduces interrupt latency by avoiding unnecessary saving and restoring of context between interrupts

B It disables all interrupts to prevent nesting

C It increases power consumption by keeping the CPU active longer

D It forces the CPU to reset after servicing each interrupt

💡 Hint

Consider what happens when one interrupt finishes and another is pending immediately.

Tail-chaining allows the CPU to switch directly from one interrupt handler to another without restoring the main program context in between, reducing latency and overhead.

❓ Comparison

expert

Comparing NVIC Software Trigger and Hardware Interrupts

Which statement correctly compares software-triggered interrupts using NVIC_STIR and hardware interrupts in ARM Cortex-M NVIC?

A Software-triggered interrupts require external hardware signals to activate

B Hardware interrupts cannot be masked or prioritized by NVIC

C Software-triggered interrupts via NVIC_STIR can simulate hardware interrupts but do not have physical external signals and can be triggered anytime by software

D NVIC_STIR disables hardware interrupts when used

💡 Hint

Think about the difference between software and hardware sources of interrupts.

NVIC_STIR allows software to trigger interrupts as if they came from hardware, but these interrupts have no physical external source and can be triggered anytime by software. Hardware interrupts come from external or internal hardware events. Both are managed by NVIC for priority and masking.

Practice

1. What is the main purpose of the NVIC's priority grouping feature?

easy

A. To disable all interrupts at once

B. To balance between pre-emption priority and subpriority levels

C. To increase the clock speed of the processor

D. To reset the microcontroller

Solution

1. Step 1: Understand NVIC priority grouping

   Priority grouping allows dividing interrupt priority into pre-emption priority and subpriority.

2. Step 2: Identify the purpose of balancing priorities

   This balance controls which interrupts can pre-empt others and which are handled in order if priorities are equal.

3. Final Answer:

   To balance between pre-emption priority and subpriority levels -> Option B

4. Quick Check:

   Priority grouping = Balancing priorities [OK]

Hint: Priority grouping splits interrupt priority levels [OK]

Common Mistakes:

• Confusing priority grouping with disabling interrupts
• Thinking it changes processor speed
• Assuming it resets the device

2. Which of the following is the correct way to enable an interrupt in NVIC?

easy

A. NVIC_DisableIRQ(IRQn);

B. NVIC_SetPriority(IRQn, priority);

C. NVIC_EnableIRQ(IRQn);

D. NVIC_ClearPendingIRQ(IRQn);

Solution

1. Step 1: Identify function to enable interrupts

   The function NVIC_EnableIRQ(IRQn) is used to enable a specific interrupt.

2. Step 2: Differentiate from other NVIC functions

   NVIC_DisableIRQ disables interrupts, SetPriority sets priority, ClearPendingIRQ clears pending flags.

3. Final Answer:

   NVIC_EnableIRQ(IRQn); -> Option C

4. Quick Check:

   Enable interrupt = NVIC_EnableIRQ [OK]

Hint: Enable interrupts with NVIC_EnableIRQ function [OK]

Common Mistakes:

• Using NVIC_DisableIRQ to enable interrupts
• Confusing priority setting with enabling
• Clearing pending interrupts instead of enabling

3. Consider the following code snippet:

NVIC_SetPriorityGrouping(3);
NVIC_SetPriority(IRQn, NVIC_EncodePriority(3, 1, 2));

What does this code do?

medium

A. Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn

B. Disables IRQn interrupt

C. Enables IRQn interrupt with default priority

D. Resets priority grouping to default

Solution

1. Step 1: Analyze NVIC_SetPriorityGrouping(3)

   This sets the priority grouping to 3, defining how many bits are for pre-emption and subpriority.

2. Step 2: Decode NVIC_SetPriority call

   NVIC_EncodePriority(3, 1, 2) encodes pre-emption priority 1 and subpriority 2 according to grouping 3, then assigns it to IRQn.

3. Final Answer:

   Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn -> Option A

4. Quick Check:

   Priority grouping 3 + encoded priority = Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn [OK]

Hint: Priority grouping affects encoding of priorities [OK]

Common Mistakes:

• Assuming it disables or enables interrupts
• Ignoring priority encoding details
• Confusing priority grouping with resetting

4. A developer wrote this code to disable an interrupt but it does not work:

NVIC_EnableIRQ(IRQn);

What is the error?

medium

A. The function NVIC_EnableIRQ enables, not disables, interrupts

B. IRQn is not a valid interrupt number

C. NVIC_DisableIRQ should be called before NVIC_EnableIRQ

D. Priority must be set before disabling interrupts

Solution

1. Step 1: Understand function purpose

   NVIC_EnableIRQ enables the interrupt, so using it to disable is incorrect.

2. Step 2: Identify correct function to disable

   NVIC_DisableIRQ should be used to disable interrupts, not NVIC_EnableIRQ.

3. Final Answer:

   The function NVIC_EnableIRQ enables, not disables, interrupts -> Option A

4. Quick Check:

   EnableIRQ enables, not disables [OK]

Hint: EnableIRQ enables; use DisableIRQ to disable [OK]

Common Mistakes:

• Confusing enable and disable functions
• Assuming priority affects enabling/disabling
• Thinking order of calls disables interrupts

5. You want to ensure that a critical interrupt always pre-empts others regardless of subpriority. Which NVIC configuration achieves this?

hard

A. Use NVIC_DisableIRQ on all other interrupts

B. Set all interrupts to the same priority level

C. Disable subpriority by setting it to maximum value

D. Set priority grouping to allocate all bits to pre-emption priority and zero to subpriority

Solution

1. Step 1: Understand priority grouping effect

   Setting priority grouping to allocate all bits to pre-emption priority means subpriority is zero, so pre-emption controls interrupt order fully.

2. Step 2: Confirm this ensures critical interrupt pre-empts others

   With no subpriority bits, the critical interrupt's pre-emption priority dominates, allowing it to always pre-empt.

3. Final Answer:

   Set priority grouping to allocate all bits to pre-emption priority and zero to subpriority -> Option D

4. Quick Check:

   All bits to pre-emption priority = critical pre-emption [OK]

Hint: Maximize pre-emption bits to ensure critical interrupt priority [OK]

Common Mistakes:

• Thinking disabling subpriority means setting it high
• Assuming same priority levels allow pre-emption
• Disabling other interrupts is not practical