NVIC advanced features in ARM Architecture - Cheat Sheet & Quick Revision

Recall & Review

beginner

What does NVIC stand for and what is its primary role in ARM Cortex-M processors?

NVIC stands for Nested Vectored Interrupt Controller. Its primary role is to manage interrupts and exceptions efficiently, allowing the processor to respond quickly to events.

intermediate

Explain the concept of interrupt priority grouping in NVIC.

Interrupt priority grouping allows dividing the priority field into group priority and subpriority. This helps decide which interrupt to serve first and how to handle interrupts of the same group priority.

intermediate

What is tail-chaining in NVIC and why is it useful?

Tail-chaining is a feature where the NVIC automatically switches to the next pending interrupt without restoring the context of the previous interrupt. This reduces latency and speeds up interrupt handling.

advanced

Describe the concept of late-arriving interrupt in NVIC.

A late-arriving interrupt occurs when a higher priority interrupt arrives while the processor is finishing a lower priority interrupt. NVIC can preempt the current interrupt to handle the higher priority one immediately.

beginner

How does NVIC support dynamic interrupt enabling and disabling?

NVIC allows software to enable or disable interrupts dynamically by setting or clearing bits in specific registers. This helps control which interrupts are active at any time.

What feature of NVIC allows it to handle multiple interrupts efficiently by automatically switching without restoring context?

A Late-arriving interrupt

B Priority grouping

C Tail-chaining

D Dynamic enabling

Tail-chaining lets NVIC switch to the next interrupt quickly without restoring the previous context, improving efficiency.

In NVIC, what does interrupt priority grouping help to determine?

A The total number of interrupts supported

B The order of interrupt servicing and subpriority handling

C The clock speed of the processor

D The memory size for interrupt vectors

Priority grouping divides priorities into groups and subpriorities to decide interrupt order and handling.

What happens during a late-arriving interrupt in NVIC?

A A higher priority interrupt preempts the current one

B The current interrupt finishes before the new one starts

C The processor ignores the new interrupt

D The interrupt is queued for later

Late-arriving interrupts allow higher priority interrupts to preempt lower priority ones immediately.

How can software control which interrupts are active in NVIC?

A By resetting the processor

B By changing the processor clock speed

C By modifying the memory map

D By enabling or disabling interrupts dynamically via registers

Software can set or clear bits in NVIC registers to enable or disable interrupts dynamically.

Which NVIC feature helps reduce interrupt latency by avoiding unnecessary context saves?

A Tail-chaining

B Priority grouping

C Late-arriving interrupt

D Dynamic enabling

Tail-chaining reduces latency by skipping context restore when switching interrupts.

Explain how NVIC manages interrupt priorities and what benefits this provides in real-time systems.

Think about how NVIC decides which interrupt to handle first and how it can interrupt another.

Describe the concepts of tail-chaining and late-arriving interrupts in NVIC and how they improve processor responsiveness.

Focus on how NVIC handles multiple interrupts quickly and efficiently.

Practice

1. What is the main purpose of the NVIC's priority grouping feature?

easy

A. To disable all interrupts at once

B. To balance between pre-emption priority and subpriority levels

C. To increase the clock speed of the processor

D. To reset the microcontroller

Solution

1. Step 1: Understand NVIC priority grouping

   Priority grouping allows dividing interrupt priority into pre-emption priority and subpriority.

2. Step 2: Identify the purpose of balancing priorities

   This balance controls which interrupts can pre-empt others and which are handled in order if priorities are equal.

3. Final Answer:

   To balance between pre-emption priority and subpriority levels -> Option B

4. Quick Check:

   Priority grouping = Balancing priorities [OK]

Hint: Priority grouping splits interrupt priority levels [OK]

Common Mistakes:

• Confusing priority grouping with disabling interrupts
• Thinking it changes processor speed
• Assuming it resets the device

2. Which of the following is the correct way to enable an interrupt in NVIC?

easy

A. NVIC_DisableIRQ(IRQn);

B. NVIC_SetPriority(IRQn, priority);

C. NVIC_EnableIRQ(IRQn);

D. NVIC_ClearPendingIRQ(IRQn);

Solution

1. Step 1: Identify function to enable interrupts

   The function NVIC_EnableIRQ(IRQn) is used to enable a specific interrupt.

2. Step 2: Differentiate from other NVIC functions

   NVIC_DisableIRQ disables interrupts, SetPriority sets priority, ClearPendingIRQ clears pending flags.

3. Final Answer:

   NVIC_EnableIRQ(IRQn); -> Option C

4. Quick Check:

   Enable interrupt = NVIC_EnableIRQ [OK]

Hint: Enable interrupts with NVIC_EnableIRQ function [OK]

Common Mistakes:

• Using NVIC_DisableIRQ to enable interrupts
• Confusing priority setting with enabling
• Clearing pending interrupts instead of enabling

3. Consider the following code snippet:

NVIC_SetPriorityGrouping(3);
NVIC_SetPriority(IRQn, NVIC_EncodePriority(3, 1, 2));

What does this code do?

medium

A. Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn

B. Disables IRQn interrupt

C. Enables IRQn interrupt with default priority

D. Resets priority grouping to default

Solution

1. Step 1: Analyze NVIC_SetPriorityGrouping(3)

   This sets the priority grouping to 3, defining how many bits are for pre-emption and subpriority.

2. Step 2: Decode NVIC_SetPriority call

   NVIC_EncodePriority(3, 1, 2) encodes pre-emption priority 1 and subpriority 2 according to grouping 3, then assigns it to IRQn.

3. Final Answer:

   Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn -> Option A

4. Quick Check:

   Priority grouping 3 + encoded priority = Sets priority grouping to 3 and assigns pre-emption priority 1 and subpriority 2 to IRQn [OK]

Hint: Priority grouping affects encoding of priorities [OK]

Common Mistakes:

• Assuming it disables or enables interrupts
• Ignoring priority encoding details
• Confusing priority grouping with resetting

4. A developer wrote this code to disable an interrupt but it does not work:

NVIC_EnableIRQ(IRQn);

What is the error?

medium

A. The function NVIC_EnableIRQ enables, not disables, interrupts

B. IRQn is not a valid interrupt number

C. NVIC_DisableIRQ should be called before NVIC_EnableIRQ

D. Priority must be set before disabling interrupts

Solution

1. Step 1: Understand function purpose

   NVIC_EnableIRQ enables the interrupt, so using it to disable is incorrect.

2. Step 2: Identify correct function to disable

   NVIC_DisableIRQ should be used to disable interrupts, not NVIC_EnableIRQ.

3. Final Answer:

   The function NVIC_EnableIRQ enables, not disables, interrupts -> Option A

4. Quick Check:

   EnableIRQ enables, not disables [OK]

Hint: EnableIRQ enables; use DisableIRQ to disable [OK]

Common Mistakes:

• Confusing enable and disable functions
• Assuming priority affects enabling/disabling
• Thinking order of calls disables interrupts

5. You want to ensure that a critical interrupt always pre-empts others regardless of subpriority. Which NVIC configuration achieves this?

hard

A. Use NVIC_DisableIRQ on all other interrupts

B. Set all interrupts to the same priority level

C. Disable subpriority by setting it to maximum value

D. Set priority grouping to allocate all bits to pre-emption priority and zero to subpriority

Solution

1. Step 1: Understand priority grouping effect

   Setting priority grouping to allocate all bits to pre-emption priority means subpriority is zero, so pre-emption controls interrupt order fully.

2. Step 2: Confirm this ensures critical interrupt pre-empts others

   With no subpriority bits, the critical interrupt's pre-emption priority dominates, allowing it to always pre-empt.

3. Final Answer:

   Set priority grouping to allocate all bits to pre-emption priority and zero to subpriority -> Option D

4. Quick Check:

   All bits to pre-emption priority = critical pre-emption [OK]

Hint: Maximize pre-emption bits to ensure critical interrupt priority [OK]

Common Mistakes:

• Thinking disabling subpriority means setting it high
• Assuming same priority levels allow pre-emption
• Disabling other interrupts is not practical