Interrupt enable and disable in ARM Architecture - Step-by-Step Execution

Concept Flow - Interrupt enable and disable

Start

↓

Check Interrupt Status

↓

Enable Interrupt?

Yes→Set Enable Bit

↓

Interrupts Enabled

↓

Disable Interrupt?

Yes→Clear Enable Bit

↓

Interrupts Disabled

↓

Continue Normal Execution

This flow shows checking the interrupt status, then enabling or disabling interrupts by setting or clearing the enable bit, and continuing normal execution.

Execution Sample

ARM Architecture

CPSIE i  // Enable interrupts
// ... some code ...
CPSID i  // Disable interrupts

This code enables interrupts, runs some code, then disables interrupts.

Analysis Table

Step	Instruction	Action	Interrupt Enable Bit	Effect
1	CPSIE i	Set interrupt enable bit to 1	1	Interrupts enabled, CPU can respond to interrupts
2	// ... some code ...	Normal code execution	1	Interrupts remain enabled
3	CPSID i	Clear interrupt enable bit to 0	0	Interrupts disabled, CPU ignores interrupts
4	Continue execution	Normal code runs without interrupts	0	No interrupts will be handled

💡 Interrupt enable bit is 0, so interrupts are disabled and CPU ignores interrupt requests

State Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	Final
Interrupt Enable Bit	0	1	1	0	0

Key Insights - 3 Insights

Why does the CPU ignore interrupts after CPSID i?

Because CPSID i clears the interrupt enable bit to 0 (see execution_table step 3), so interrupts are disabled.

Does enabling interrupts immediately trigger an interrupt?

No, enabling interrupts (step 1) just allows the CPU to respond to interrupts if they occur later.

What happens if interrupts are disabled during critical code?

Disabling interrupts (step 3) prevents interrupt handling, so critical code runs without interruption.

Visual Quiz - 3 Questions

Look at the execution_table at step 1. What is the value of the Interrupt Enable Bit?

A 1

B 0

C Undefined

D 2

💡 Hint

Check the Interrupt Enable Bit column at step 1 in the execution_table.

At which step does the CPU stop responding to interrupts?

A Step 1

B Step 3

C Step 2

D Step 4

💡 Hint

Look at the Effect column in execution_table for when interrupts are disabled.

If CPSIE i was not called at step 1, what would be the Interrupt Enable Bit after step 2?

A 1

B Depends on previous state

C 0

D Cannot tell

💡 Hint

Refer to variable_tracker and execution_table to see how CPSIE i affects the bit.

Concept Snapshot

Interrupt enable and disable control whether the CPU responds to interrupts.
Use CPSIE i to enable interrupts (sets enable bit to 1).
Use CPSID i to disable interrupts (clears enable bit to 0).
When disabled, CPU ignores interrupt requests.
Enable interrupts before critical code ends to allow normal interrupt handling.

Full Transcript

This lesson shows how interrupts are enabled and disabled in ARM architecture using CPSIE i and CPSID i instructions. Initially, interrupts are disabled (enable bit 0). When CPSIE i runs, it sets the enable bit to 1, allowing the CPU to respond to interrupts. The CPU continues normal execution with interrupts enabled. Later, CPSID i clears the enable bit to 0, disabling interrupts so the CPU ignores interrupt requests. This is useful to protect critical code sections from interruption. The variable Interrupt Enable Bit changes from 0 to 1 and back to 0 as these instructions execute. Understanding this helps control when the CPU can be interrupted.