Interrupt enable and disable in ARM Architecture - Time & Space Complexity
When enabling or disabling interrupts in ARM architecture, it is important to understand how the time taken changes as the number of instructions or operations grows.
We want to know how the execution time scales when these interrupt control instructions are used repeatedly.
Analyze the time complexity of the following ARM instructions that enable and disable interrupts.
CPSID i // Disable IRQ interrupts
CPSIE i // Enable IRQ interrupts
NOP // No operation (wait)
CPSID f // Disable FIQ interrupts
CPSIE f // Enable FIQ interrupts
This code snippet shows simple instructions to turn interrupts on or off in ARM processors.
Look for instructions that repeat or cause delays.
- Primary operation: Each CPSID or CPSIE instruction executes once per call.
- How many times: These instructions run a fixed number of times, not inside loops.
Since each interrupt enable or disable instruction runs once, the total time grows directly with how many times you call them.
| Input Size (n) | Approx. Operations |
|---|---|
| 10 | 10 instructions |
| 100 | 100 instructions |
| 1000 | 1000 instructions |
Pattern observation: The time increases in a straight line as you add more enable/disable calls.
Time Complexity: O(n)
This means the time to enable or disable interrupts grows directly with how many times you do it.
[X] Wrong: "Enabling or disabling interrupts takes constant time no matter how many times it is done."
[OK] Correct: Each instruction runs once per call, so if you do it multiple times, total time adds up linearly.
Understanding how simple instructions like interrupt control scale with usage helps you reason about system responsiveness and performance in real devices.
"What if the interrupt enable/disable instructions were placed inside a loop that runs n times? How would the time complexity change?"