Program Status Register (PSR) in ARM Architecture - Step-by-Step Execution

Concept Flow - Program Status Register (PSR)

Instruction Executes

↓

PSR Updated

↓

Flags Set or Cleared

↓

Processor State Changed if Needed

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Next Instruction Uses PSR Status

The PSR updates after each instruction to reflect flags and processor state, which influence future instruction behavior.

Execution Sample

ARM Architecture

MOVS R0, #0
CMP R0, #0
BNE label
; PSR updated after CMP

This code moves 0 into R0, compares R0 with 0, and branches if not equal, showing PSR flags update after CMP.

Analysis Table

Step	Instruction	PSR Flags Before	Operation	PSR Flags After	Effect
1	MOVS R0, #0	N=0 Z=0 C=0 V=0	Set R0=0	N=0 Z=1 C=0 V=0	Zero flag set because R0=0
2	CMP R0, #0	N=0 Z=1 C=0 V=0	Compare R0 with 0	N=0 Z=1 C=1 V=0	Zero flag remains, Carry set for equality
3	BNE label	N=0 Z=1 C=1 V=0	Branch if Not Equal (Z=0)	N=0 Z=1 C=1 V=0	No branch taken because Z=1 (equal)
4	End	N=0 Z=1 C=1 V=0	Execution stops	N=0 Z=1 C=1 V=0	Program continues sequentially

💡 Execution stops after BNE because condition not met (Z=1 means equal, so no branch)

State Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	Final
R0	undefined	0	0	0	0
N Flag	0	0	0	0	0
Z Flag	0	1	1	1	1
C Flag	0	0	1	1	1
V Flag	0	0	0	0	0

Key Insights - 3 Insights

Why does the Zero (Z) flag become 1 after MOVS R0, #0 even though MOVS does not compare?

MOVS with immediate zero sets the Zero flag because the result is zero. See execution_table row 1 where Z changes from 0 to 1.

Why does the BNE instruction not branch even though it is a branch instruction?

BNE branches only if Zero flag is 0 (not equal). Here Z=1 after CMP, so no branch occurs. See execution_table row 3.

What does the Carry (C) flag indicate after CMP instruction?

Carry flag is set to 1 after CMP if the first value is greater or equal. Here, R0 equals 0, so C=1. See execution_table row 2.

Visual Quiz - 3 Questions

Look at the execution_table at Step 2. What is the value of the Zero (Z) flag after CMP?

A Undefined

B 0

C 1

D Cannot tell

💡 Hint

Check the 'PSR Flags After' column in row 2 of execution_table.

At which step does the program decide not to branch?

A Step 3

B Step 2

C Step 1

D Step 4

💡 Hint

Look at the 'Effect' column in execution_table row 3.

If R0 was set to 1 instead of 0 in Step 1, what would happen at Step 3?

A Branch would not be taken

B Branch would be taken

C Program would crash

D No change in behavior

💡 Hint

Changing R0 affects CMP result and Zero flag; check how BNE depends on Z flag in execution_table.

Concept Snapshot

Program Status Register (PSR) holds flags (N, Z, C, V) updated after instructions.
Flags reflect results like zero, negative, carry, overflow.
Branch instructions use PSR flags to decide flow.
PSR updates after each instruction that affects flags.
Understanding PSR helps predict program decisions.

Full Transcript

The Program Status Register (PSR) in ARM architecture updates after each instruction to reflect the current state of the processor. It holds flags such as Negative (N), Zero (Z), Carry (C), and Overflow (V). For example, after moving zero into a register, the Zero flag is set. Comparing values updates flags based on the result. Branch instructions check these flags to decide whether to jump or continue sequentially. This trace showed MOVS, CMP, and BNE instructions updating and using PSR flags step-by-step, helping understand how processor decisions depend on PSR.

Practice

1. What is the primary purpose of the Program Status Register (PSR) in ARM architecture?

easy

A. To hold flags that indicate the results of operations and control processor modes

B. To store the address of the next instruction to execute

C. To manage memory allocation for programs

D. To handle input/output operations directly

Solution

1. Step 1: Understand the role of PSR

   The PSR contains flags like zero, carry, negative, and overflow that reflect the outcome of arithmetic or logical operations.

2. Step 2: Identify PSR's control function

   It also controls processor modes such as user mode or interrupt mode, affecting how the processor behaves.

3. Final Answer:

   To hold flags that indicate the results of operations and control processor modes -> Option A

4. Quick Check:

   PSR = Flags + Mode Control [OK]

Hint: PSR holds flags and modes, not addresses or memory [OK]

Common Mistakes:

• Confusing PSR with program counter
• Thinking PSR manages memory
• Assuming PSR handles I/O directly

2. Which of the following is a correct way to refer to the condition flags in the ARM Program Status Register (PSR)?

easy

A. PC, LR, SP

B. IRQ, FIQ, SVC

C. R0, R1, R2

D. N, Z, C, V

Solution

1. Step 1: Identify condition flags in PSR

   The condition flags in PSR are Negative (N), Zero (Z), Carry (C), and Overflow (V).

2. Step 2: Eliminate unrelated registers and modes

   PC, LR, SP are registers, not flags; IRQ, FIQ, SVC are interrupt modes; R0-R2 are general-purpose registers.

3. Final Answer:

   N, Z, C, V -> Option D

4. Quick Check:

   Flags = N, Z, C, V [OK]

Hint: Remember flags as N, Z, C, V in PSR [OK]

Common Mistakes:

• Mixing registers with flags
• Confusing interrupt modes with flags
• Using general-purpose registers as flags

3. Consider the following ARM assembly snippet that updates the PSR flags after an addition:

ADD R0, R1, R2
CMP R0, #0

What will the Zero (Z) flag in the PSR be if the result in R0 is zero?

medium

A. Cleared to 0

B. Set to 0

C. Set to 1

D. Undefined

Solution

1. Step 1: Understand the CMP instruction effect

   CMP compares R0 with zero and sets the Zero flag if R0 equals zero.

2. Step 2: Analyze the Zero flag behavior

   If R0 is zero, the Zero flag (Z) is set to 1 to indicate equality.

3. Final Answer:

   Set to 1 -> Option C

4. Quick Check:

   R0 == 0 -> Z = 1 [OK]

Hint: CMP sets Z=1 when compared value equals zero [OK]

Common Mistakes:

• Assuming Z flag clears on zero result
• Confusing CMP with ADD effect on flags
• Thinking flags remain unchanged

4. An ARM program tries to update the PSR flags using the instruction:

ADD R0, R1, R2

but the flags are not updated. What is the likely cause?

medium

A. The processor is in user mode where flags can't change

B. The instruction should be ADD{S} R0, R1, R2 to update flags

C. The registers R1 and R2 are invalid

D. The PSR is read-only and cannot be changed

Solution

1. Step 1: Check instruction syntax for flag update

   In ARM, to update PSR flags after arithmetic, the instruction must include the 'S' suffix (e.g., ADDS) to set flags.

2. Step 2: Understand default behavior without 'S'

   Without 'S', the instruction performs addition but does not update the condition flags in PSR.

3. Final Answer:

   The instruction should be ADD{S} R0, R1, R2 to update flags -> Option B

4. Quick Check:

   Use ADDS to update PSR flags [OK]

Hint: Add 'S' suffix to update PSR flags after arithmetic [OK]

Common Mistakes:

• Thinking PSR is read-only
• Assuming all ADD update flags by default
• Blaming invalid registers

5. You want to write an ARM assembly routine that branches to a label error_handler only if the Negative (N) flag in the PSR is set after a subtraction. Which instruction correctly checks this condition?

hard

A. BMI error_handler

B. BNE error_handler

C. BEQ error_handler

D. BVS error_handler

Solution

1. Step 1: Understand the meaning of condition codes

   BNE branches if Zero flag is clear; BEQ if Zero flag is set; BVS if Overflow flag is set; BMI if Negative flag is set.

2. Step 2: Match Negative flag condition to branch

   Since we want to branch when Negative flag (N) is set, the correct instruction is BMI (Branch if Minus).

3. Final Answer:

   BMI error_handler -> Option A

4. Quick Check:

   Negative flag set -> use BMI [OK]

Hint: BMI branches when Negative flag is set [OK]

Common Mistakes:

• Using BNE or BEQ which check Zero flag
• Confusing Overflow flag with Negative flag
• Choosing BVS which checks Overflow