Program Status Register (PSR) in ARM Architecture - Practice Problems & Coding Challenges

Challenge - 5 Problems

📋 Factual

intermediate

Understanding the PSR Flags

Which flag in the ARM Program Status Register (PSR) indicates that the last arithmetic operation resulted in zero?

A Z flag (Zero)

B V flag (Overflow)

C C flag (Carry)

D N flag (Negative)

💡 Hint

Think about which flag signals a zero result after an operation.

The Z flag in the PSR is set when the result of an arithmetic or logical operation is zero.

🧠 Conceptual

intermediate

PSR Mode Bits Purpose

What is the primary purpose of the mode bits in the ARM Program Status Register (PSR)?

A To hold the program counter value

B To store the result of the last arithmetic operation

C To control the interrupt priority level

D To indicate the current processor operating mode

💡 Hint

Consider what the processor needs to know about its current state or context.

The mode bits in the PSR specify the current processor mode, such as User, FIQ, IRQ, Supervisor, etc.

🔍 Analysis

advanced

Effect of Changing the Interrupt Disable Bits

What happens if the I (IRQ disable) bit in the ARM PSR is set to 1 during program execution?

A IRQ interrupts are disabled, preventing normal interrupts

B FIQ interrupts are disabled, preventing fast interrupts

C All interrupts are enabled, allowing normal operation

D Processor enters a low-power sleep mode

💡 Hint

Recall the difference between I and F bits in the PSR.

Setting the I bit disables IRQ interrupts, which are the normal interrupt requests, while F bit controls FIQ interrupts.

❓ Comparison

advanced

Difference Between CPSR and SPSR

Which statement correctly describes the difference between the Current Program Status Register (CPSR) and the Saved Program Status Register (SPSR) in ARM architecture?

A CPSR is used only in user mode; SPSR is used only in system mode

B CPSR holds the current processor state; SPSR holds the saved state during exceptions

C CPSR stores interrupt vectors; SPSR stores general-purpose registers

D CPSR and SPSR are identical and interchangeable

💡 Hint

Think about what happens when an exception occurs.

The CPSR contains the current processor status, while the SPSR saves the CPSR state when an exception occurs, allowing restoration after handling.

❓ Reasoning

expert

Interpreting PSR Bit Patterns

Given the 32-bit value of the ARM CPSR as 0x600001D3, which of the following statements is true about the processor state?

A Processor is in User mode with all interrupts enabled

B Processor is in System mode with IRQ disabled and FIQ enabled

C Processor is in Supervisor mode with IRQ and FIQ disabled

D Processor is in Abort mode with interrupts enabled

💡 Hint

Decode the mode bits and interrupt disable bits from the hex value.

The mode bits (lowest 5 bits) 0x13 indicate Supervisor mode. Bits 7 (I) and 6 (F) are set (bits 6 and 7 in 0xD3), disabling IRQ and FIQ.

Practice

1. What is the primary purpose of the Program Status Register (PSR) in ARM architecture?

easy

A. To hold flags that indicate the results of operations and control processor modes

B. To store the address of the next instruction to execute

C. To manage memory allocation for programs

D. To handle input/output operations directly

Solution

1. Step 1: Understand the role of PSR

   The PSR contains flags like zero, carry, negative, and overflow that reflect the outcome of arithmetic or logical operations.

2. Step 2: Identify PSR's control function

   It also controls processor modes such as user mode or interrupt mode, affecting how the processor behaves.

3. Final Answer:

   To hold flags that indicate the results of operations and control processor modes -> Option A

4. Quick Check:

   PSR = Flags + Mode Control [OK]

Hint: PSR holds flags and modes, not addresses or memory [OK]

Common Mistakes:

• Confusing PSR with program counter
• Thinking PSR manages memory
• Assuming PSR handles I/O directly

2. Which of the following is a correct way to refer to the condition flags in the ARM Program Status Register (PSR)?

easy

A. PC, LR, SP

B. IRQ, FIQ, SVC

C. R0, R1, R2

D. N, Z, C, V

Solution

1. Step 1: Identify condition flags in PSR

   The condition flags in PSR are Negative (N), Zero (Z), Carry (C), and Overflow (V).

2. Step 2: Eliminate unrelated registers and modes

   PC, LR, SP are registers, not flags; IRQ, FIQ, SVC are interrupt modes; R0-R2 are general-purpose registers.

3. Final Answer:

   N, Z, C, V -> Option D

4. Quick Check:

   Flags = N, Z, C, V [OK]

Hint: Remember flags as N, Z, C, V in PSR [OK]

Common Mistakes:

• Mixing registers with flags
• Confusing interrupt modes with flags
• Using general-purpose registers as flags

3. Consider the following ARM assembly snippet that updates the PSR flags after an addition:

ADD R0, R1, R2
CMP R0, #0

What will the Zero (Z) flag in the PSR be if the result in R0 is zero?

medium

A. Cleared to 0

B. Set to 0

C. Set to 1

D. Undefined

Solution

1. Step 1: Understand the CMP instruction effect

   CMP compares R0 with zero and sets the Zero flag if R0 equals zero.

2. Step 2: Analyze the Zero flag behavior

   If R0 is zero, the Zero flag (Z) is set to 1 to indicate equality.

3. Final Answer:

   Set to 1 -> Option C

4. Quick Check:

   R0 == 0 -> Z = 1 [OK]

Hint: CMP sets Z=1 when compared value equals zero [OK]

Common Mistakes:

• Assuming Z flag clears on zero result
• Confusing CMP with ADD effect on flags
• Thinking flags remain unchanged

4. An ARM program tries to update the PSR flags using the instruction:

ADD R0, R1, R2

but the flags are not updated. What is the likely cause?

medium

A. The processor is in user mode where flags can't change

B. The instruction should be ADD{S} R0, R1, R2 to update flags

C. The registers R1 and R2 are invalid

D. The PSR is read-only and cannot be changed

Solution

1. Step 1: Check instruction syntax for flag update

   In ARM, to update PSR flags after arithmetic, the instruction must include the 'S' suffix (e.g., ADDS) to set flags.

2. Step 2: Understand default behavior without 'S'

   Without 'S', the instruction performs addition but does not update the condition flags in PSR.

3. Final Answer:

   The instruction should be ADD{S} R0, R1, R2 to update flags -> Option B

4. Quick Check:

   Use ADDS to update PSR flags [OK]

Hint: Add 'S' suffix to update PSR flags after arithmetic [OK]

Common Mistakes:

• Thinking PSR is read-only
• Assuming all ADD update flags by default
• Blaming invalid registers

5. You want to write an ARM assembly routine that branches to a label error_handler only if the Negative (N) flag in the PSR is set after a subtraction. Which instruction correctly checks this condition?

hard

A. BMI error_handler

B. BNE error_handler

C. BEQ error_handler

D. BVS error_handler

Solution

1. Step 1: Understand the meaning of condition codes

   BNE branches if Zero flag is clear; BEQ if Zero flag is set; BVS if Overflow flag is set; BMI if Negative flag is set.

2. Step 2: Match Negative flag condition to branch

   Since we want to branch when Negative flag (N) is set, the correct instruction is BMI (Branch if Minus).

3. Final Answer:

   BMI error_handler -> Option A

4. Quick Check:

   Negative flag set -> use BMI [OK]

Hint: BMI branches when Negative flag is set [OK]

Common Mistakes:

• Using BNE or BEQ which check Zero flag
• Confusing Overflow flag with Negative flag
• Choosing BVS which checks Overflow