Program Status Register (PSR) in ARM Architecture - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the Program Status Register (PSR) in ARM architecture?

The PSR is a special register in ARM processors that holds important information about the current state of the processor, including condition flags, interrupt status, and processor mode.

intermediate

Name the three main parts of the Program Status Register (PSR).

The PSR consists of three parts: the Application Program Status Register (APSR), the Interrupt Program Status Register (IPSR), and the Execution Program Status Register (EPSR).

beginner

What do the condition flags in the PSR indicate?

Condition flags in the PSR indicate the results of arithmetic or logical operations, such as zero result, negative result, carry out, or overflow.

intermediate

How does the PSR help in handling interrupts?

The PSR contains bits that show the current interrupt status, helping the processor know if interrupts are enabled or disabled and which interrupt is being handled.

intermediate

Why is the processor mode information in the PSR important?

Processor mode bits in the PSR tell the processor which mode it is running in, such as Thread mode or Handler mode, which controls access to system resources and privileges.

What does the 'N' flag in the PSR represent?

A Negative result

B Zero result

C Carry out

D Overflow

The 'N' flag in the PSR indicates that the result of an operation was negative.

Which part of the PSR holds the processor mode bits?

A EPSR

B IPSR

C All parts combined

D APSR

Processor mode bits are part of the combined PSR, not just the IPSR. The IPSR holds the current exception number, while the mode bits are in the combined PSR.

What information does the IPSR part of the PSR provide?

A Current interrupt number

B Condition flags

C Processor mode

D Execution state

The Interrupt Program Status Register (IPSR) holds the current interrupt number being handled.

Which PSR flag indicates an overflow in arithmetic operations?

A N flag

B C flag

C Z flag

D V flag

The 'V' flag in the PSR indicates an overflow occurred during an arithmetic operation.

Why is the PSR important for conditional instructions?

A It stores the instruction address

B It holds condition flags used to decide if instructions run

C It manages memory access

D It controls clock speed

The PSR holds condition flags that conditional instructions check to decide whether to execute.

Explain the role of the Program Status Register (PSR) in ARM processors.

Think about what information the processor needs to keep track of during execution.

Describe the three main parts of the PSR and what each part represents.

Divide the PSR into its components and explain their functions.

Practice

1. What is the primary purpose of the Program Status Register (PSR) in ARM architecture?

easy

A. To hold flags that indicate the results of operations and control processor modes

B. To store the address of the next instruction to execute

C. To manage memory allocation for programs

D. To handle input/output operations directly

Solution

1. Step 1: Understand the role of PSR

   The PSR contains flags like zero, carry, negative, and overflow that reflect the outcome of arithmetic or logical operations.

2. Step 2: Identify PSR's control function

   It also controls processor modes such as user mode or interrupt mode, affecting how the processor behaves.

3. Final Answer:

   To hold flags that indicate the results of operations and control processor modes -> Option A

4. Quick Check:

   PSR = Flags + Mode Control [OK]

Hint: PSR holds flags and modes, not addresses or memory [OK]

Common Mistakes:

• Confusing PSR with program counter
• Thinking PSR manages memory
• Assuming PSR handles I/O directly

2. Which of the following is a correct way to refer to the condition flags in the ARM Program Status Register (PSR)?

easy

A. PC, LR, SP

B. IRQ, FIQ, SVC

C. R0, R1, R2

D. N, Z, C, V

Solution

1. Step 1: Identify condition flags in PSR

   The condition flags in PSR are Negative (N), Zero (Z), Carry (C), and Overflow (V).

2. Step 2: Eliminate unrelated registers and modes

   PC, LR, SP are registers, not flags; IRQ, FIQ, SVC are interrupt modes; R0-R2 are general-purpose registers.

3. Final Answer:

   N, Z, C, V -> Option D

4. Quick Check:

   Flags = N, Z, C, V [OK]

Hint: Remember flags as N, Z, C, V in PSR [OK]

Common Mistakes:

• Mixing registers with flags
• Confusing interrupt modes with flags
• Using general-purpose registers as flags

3. Consider the following ARM assembly snippet that updates the PSR flags after an addition:

ADD R0, R1, R2
CMP R0, #0

What will the Zero (Z) flag in the PSR be if the result in R0 is zero?

medium

A. Cleared to 0

B. Set to 0

C. Set to 1

D. Undefined

Solution

1. Step 1: Understand the CMP instruction effect

   CMP compares R0 with zero and sets the Zero flag if R0 equals zero.

2. Step 2: Analyze the Zero flag behavior

   If R0 is zero, the Zero flag (Z) is set to 1 to indicate equality.

3. Final Answer:

   Set to 1 -> Option C

4. Quick Check:

   R0 == 0 -> Z = 1 [OK]

Hint: CMP sets Z=1 when compared value equals zero [OK]

Common Mistakes:

• Assuming Z flag clears on zero result
• Confusing CMP with ADD effect on flags
• Thinking flags remain unchanged

4. An ARM program tries to update the PSR flags using the instruction:

ADD R0, R1, R2

but the flags are not updated. What is the likely cause?

medium

A. The processor is in user mode where flags can't change

B. The instruction should be ADD{S} R0, R1, R2 to update flags

C. The registers R1 and R2 are invalid

D. The PSR is read-only and cannot be changed

Solution

1. Step 1: Check instruction syntax for flag update

   In ARM, to update PSR flags after arithmetic, the instruction must include the 'S' suffix (e.g., ADDS) to set flags.

2. Step 2: Understand default behavior without 'S'

   Without 'S', the instruction performs addition but does not update the condition flags in PSR.

3. Final Answer:

   The instruction should be ADD{S} R0, R1, R2 to update flags -> Option B

4. Quick Check:

   Use ADDS to update PSR flags [OK]

Hint: Add 'S' suffix to update PSR flags after arithmetic [OK]

Common Mistakes:

• Thinking PSR is read-only
• Assuming all ADD update flags by default
• Blaming invalid registers

5. You want to write an ARM assembly routine that branches to a label error_handler only if the Negative (N) flag in the PSR is set after a subtraction. Which instruction correctly checks this condition?

hard

A. BMI error_handler

B. BNE error_handler

C. BEQ error_handler

D. BVS error_handler

Solution

1. Step 1: Understand the meaning of condition codes

   BNE branches if Zero flag is clear; BEQ if Zero flag is set; BVS if Overflow flag is set; BMI if Negative flag is set.

2. Step 2: Match Negative flag condition to branch

   Since we want to branch when Negative flag (N) is set, the correct instruction is BMI (Branch if Minus).

3. Final Answer:

   BMI error_handler -> Option A

4. Quick Check:

   Negative flag set -> use BMI [OK]

Hint: BMI branches when Negative flag is set [OK]

Common Mistakes:

• Using BNE or BEQ which check Zero flag
• Confusing Overflow flag with Negative flag
• Choosing BVS which checks Overflow